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| LXT9762/9782 Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Datasheet General Description The LXT9782 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The LXT9762 offers the same features and functionality in a six-port device. This data sheet uses the singular designation "LXT97x2" to refer to both devices. The LXT97x2 interfaces multiple Serial Media Independent Interface (SMII) compliant controllers to 10BASE-T and/or 100BASE-TX media. All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The LXT97x2 provides three discrete LED drivers for each port, and eight global serial LED outputs. It supports both half- and full-duplex operation at 10 and 100 Mbps and requires only a single 3.3V power supply. Application s 100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs. Product Features s s s s s Multiple independent IEEE 802.3compliant 10/100 ports with integrated filters Proprietary Optimal Signal Processing (OSPTM) design improves SNR by 3 dB over ideal analog filters Robust baseline wander correction for improved 100BASE-TX performance 100BASE-FX fiber-optic capability on all ports Supports both auto-negotiation and legacy systems without auto-negotiation capability s s s s s s s s JTAG boundary scan Multiple Serial MII (SMII) ports for independent PHY port operation Configurable via MDIO port or external control pins Maskable interrupts Very low power consumption (400 mW per port, typical) 3.3V operation 208-pin PQFP and 272-lead BGA 0-70oC ambient temperature range As of January 15, 2001, this document replaces the Level One document LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII. Order Number: 249039-001 January 2001 Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT9762/9782 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Contents. 1.0 2.0 Preliminary Pin Assignments and Signal Descriptions ...........................10 Functional Description...........................................................................................20 2.1 Introduction..........................................................................................................20 2.1.1 OSPTM Architecture ................................................................................20 2.1.2 Comprehensive Functionality .................................................................20 Interface Descriptions..........................................................................................21 2.2.1 10/100 Network Interface .......................................................................21 2.2.2 SMII Data Interface ................................................................................22 2.2.3 Configuration Management Interface .....................................................22 Operating Requirements .....................................................................................25 2.3.1 Power Requirements..............................................................................25 2.3.2 Clock Requirements ...............................................................................25 Initialization..........................................................................................................25 2.4.1 Hardware Configuration Settings ...........................................................26 2.4.2 Reset ......................................................................................................27 2.4.3 Power-Down Mode.................................................................................28 Link Establishment ..............................................................................................28 2.5.1 Auto-Negotiation.....................................................................................28 2.5.2 Parallel Detection ...................................................................................29 Serial MII Operation ............................................................................................29 2.6.1 Reference Clock.....................................................................................31 2.6.2 SYNC Pulse ...........................................................................................31 2.6.3 Transmit Data Stream ............................................................................31 2.6.4 Receive Data Stream .............................................................................32 2.6.5 Loopback................................................................................................33 2.6.6 Collision..................................................................................................33 100 Mbps Operation............................................................................................34 2.7.1 100BASE-X Network Operations ...........................................................34 2.7.2 .100BASE-X Protocol Sublayer Operations ...........................................35 10 Mbps Operation..............................................................................................39 2.8.1 10T Preamble Handling..........................................................................40 2.8.2 10T Dribble Bits......................................................................................40 2.8.3 10T Link Test..........................................................................................40 2.8.4 10T Jabber .............................................................................................40 Monitoring Operations .........................................................................................40 2.9.1 Serial LED Functions..............................................................................40 2.9.2 Per-Port LED Driver Functions ...............................................................42 2.9.3 Monitoring Auto-Negotiation...................................................................43 2.9.4 Using the Quick Status Register ............................................................44 Boundary Scan (JTAG1149.1) Functions............................................................44 2.10.1 Boundary Scan Interface........................................................................44 2.10.2 State Machine ........................................................................................45 2.10.3 Instruction Register ................................................................................45 2.10.4 Boundary Scan Register ........................................................................45 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Datasheet 3 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 3.0 Application Information......................................................................................... 46 3.1 Design Recommendations .................................................................................. 46 3.1.1 General Design Guidelines .................................................................... 46 3.1.2 Power Supply Filtering ........................................................................... 46 3.1.3 Power and Ground Plane Layout Considerations .................................. 47 3.1.4 MII Terminations .................................................................................... 47 3.1.5 The RBIAS Pin ....................................................................................... 47 3.1.6 The Twisted-Pair Interface ..................................................................... 47 3.1.7 The Fiber Interface................................................................................. 48 Typical Application Circuits ................................................................................. 49 3.2 4.0 5.0 6.0 Test Specifications.................................................................................................. 53 Register Definitions ................................................................................................ 63 Package Specifications ......................................................................................... 77 4 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 LXT 9782 Block Diagram ...................................................................................... 9 LXT9782HC (PQFP) Preliminary Pin Assignments............................................10 LXT9782BC (PBGA) Preliminary Pin Assignments............................................11 LXT9762HC (PQFP) Preliminary Pin Assignments ............................................12 LXT97x2 Interfaces ............................................................................................21 Port Address Scheme .........................................................................................23 Management Interface Read Frame Structure ...................................................23 Management Interface Write Frame Structure ...................................................24 Interrupt Logic ....................................................................................................24 Initialization Sequence .......................................................................................26 Hardware Control Settings .................................................................................27 Link Establishment Process ...............................................................................29 Simplified SMII Application Diagram ..................................................................30 100Mbps Serial MII Data Flow ...........................................................................31 Serial MII Transmit Synchronization ..................................................................32 Loopback Paths...................................................................................................33 Serial MII Receive Synchronization ....................................................................33 100BASE-X Frame Format ...............................................................................34 Protocol Sublayers .............................................................................................36 Serial LED Streams.............................................................................................42 LED Pulse Stretching ..........................................................................................43 Quick Status Register..........................................................................................44 Power and Ground Supply Connections ............................................................49 Typical Twisted-Pair Interface ............................................................................50 Typical Fiber Interface ........................................................................................51 Typical Serial LED Interface................................................................................52 MII Sync Timing...................................................................................................56 100BASE-TX Receive Timing .............................................................................56 SMII Output Delay Test Setup............................................................................57 100BASE-TX Transmit Timing ............................................................................57 100BASE-FX Receive Timing .............................................................................58 100BASE-FX Transmit Timing ............................................................................58 10BASE-T Receive Timing..................................................................................59 10BASE-T Transmit Timing.................................................................................59 Auto-Negotiation and Fast Link Pulse Timing ....................................................60 Fast Link Pulse Timing .......................................................................................60 MDIO Write Timing (MDIO Sourced by MAC) ....................................................61 MDIO Read Timing (MDIO Sourced by PHY) ....................................................61 Power-Up Timing ................................................................................................62 Reset and Power-Down Recovery Timing .........................................................62 PHY Identifier Bit Mapping ..................................................................................68 LXT97x2 PQFP Package Specification...............................................................77 LXT97x2 PBGA Package Specification...............................................................78 Datasheet 5 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 LXT97x2 Serial MII Signal Descriptions.............................................................. 13 LXT97x2 Signal Detect/TP Select Signal Descriptions ....................................... 14 LXT97x2 Network Interface Signal Descriptions................................................. 14 LXT97x2 JTAG Test Signal Descriptions ............................................................ 15 LXT97x2 Miscellaneous Signal Descriptions ...................................................... 15 LXT97x2 Power Supply Signal Descriptions....................................................... 16 LXT97x2 LED Signal Descriptions ...................................................................... 17 Unused Pins........................................................................................................ 19 Hardware Configuration Settings ........................................................................ 27 SMII Signal Summary ......................................................................................... 30 RX Status Encoding Bit Definitions ..................................................................... 33 4B/5B Coding ...................................................................................................... 36 BSR Mode of Operation ...................................................................................... 45 Supported JTAG Instructions .............................................................................. 45 Device ID Register .............................................................................................. 45 Magnetics Requirements .................................................................................... 48 Absolute Maximum Ratings ................................................................................ 53 Operating Conditions .......................................................................................... 53 Digital I/O Characteristics 1................................................................................. 54 Digital I/O Characteristics - SMII Pins ................................................................. 54 Required REFCLK and SYNC Characteristics.................................................... 54 100BASE-TX Transceiver Characteristics .......................................................... 55 100BASE-FX Transceiver Characteristics .......................................................... 55 10BASE-T Transceiver Characteristics............................................................... 55 MII Sync Timing Parameters ............................................................................... 56 100BASE-TX Receive Timing Parameters ......................................................... 56 100BASE-TX Transmit Timing Parameters ........................................................ 57 100BASE-FX Receive Timing Parameters ......................................................... 58 100BASE-FX Transmit Timing Parameters ........................................................ 58 10BASE-T Receive Timing Parameters.............................................................. 59 10BASE-T Transmit Timing Parameters............................................................. 59 Auto-Negotiation and Fast Link Pulse Timing Parameters ................................. 60 MDIO Timing Parameters ................................................................................... 61 Power-Up Timing Parameters............................................................................ 62 Reset and Power-Down Recovery Timing Parameters....................................... 62 Register Set ........................................................................................................ 63 Register Bit Map.................................................................................................. 64 Control Register (Address 0)............................................................................... 66 Status Register (Address 1) ................................................................................ 66 PHY Identification Register 1 (Address 2)........................................................... 67 PHY Identification Register 2 (Address 3)........................................................... 68 Auto-Negotiation Advertisement Register (Address 4) ....................................... 68 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) .............. 69 Auto-Negotiation Expansion (Address 6) ............................................................ 70 Auto-Negotiation Next Page Transmit Register (Address 7)............................... 71 Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ........... 71 Port Configuration Register (Address 16, Hex 10) .............................................. 72 Quick Status Register (Address 17, Hex 11) ...................................................... 72 Interrupt Enable Register (Address 18, Hex 12) ................................................. 73 6 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 50 51 52 53 Interrupt Status Register (Address 19, Hex 13) ..................................................74 LED Configuration Register (Address 20, Hex 14)..............................................75 Transmit Control Register #1 (Address 28).........................................................76 Transmit Control Register #2 (Address 30).........................................................76 Datasheet 7 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Revision History Revision Date Description 8 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 1. LXT 9782 Block Diagram QCLK QSTAT ADD_<4:0> MDC MDIO MDINT Management / Mode Select Logic & LED Drivers Global Functions RESET PWRDWN Clock Generator REFCLK SYNC TxSLEW<1:0> Register Set TX PCS Manchester 10 Encoder Parallel/Serial Converter Scrambler 100 & Encoder Auto Negotiation OSPTM Pulse Shaper TXDn TP Driver + + TP / Fiber Out TPFOPn TPFONn ECL Driver Mgmt Counters 8 LEDS_<7:0> LEDLAT LEDCLK 3 LED Logic Register Set SD/TPn OSPTM Port LED Configuration Serial to Parallel Converter Carrier Sense Data Valid Error Detect Clock Generator Media Select Adaptive EQ with BaseLine Wander Cancellation 100TX + + 100FX ED/CFGn_<3:1> 10 100 Manchester Decoder Decoder & Descrambler OSPTM Slicer TP / Fiber In TPFIPn TPFINn RXDn RX PCS + 10BT PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 Per-Port Functions - Datasheet 9 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 1.0 Preliminary Pin Assignments and Signal Descriptions Figure 2. LXT9782HC (PQFP) Preliminary Pin Assignments 208.......... VCCIO 207.......... QCLK 206.......... QSTAT 205.......... LED/CFG0_3 204.......... LED/CFG0_2 203.......... LED/CFG0_1 202.......... LED/CFG1_3 201.......... LED/CFG1_2 200.......... LED/CFG1_1 199.......... LED/CFG2_3 198.......... LED/CFG2_2 197.......... LED/CFG2_1 196.......... LED/CFG3_3 195.......... LED/CFG3_2 194.......... LED/CFG3_1 193.......... VCCIO 192.......... GNDD 191.......... LED/CFG4_3 190.......... LED/CFG4_2 189.......... LED/CFG4_1 188.......... LED/CFG5_3 187.......... LED/CFG5_2 186.......... LED/CFG5_1 185.......... LED/CFG6_3 184.......... LED/CFG6_2 183.......... LED/CFG6_1 182.......... LED/CFG7_3 181.......... LED/CFG7_2 180.......... LED/CFG7_1 179.......... VCCD 178.......... GNDD 177.......... LEDS0 176.......... LEDS1 175.......... LEDS2 174.......... LEDS3 173.......... LEDS4 172.......... LEDS5 171.......... LEDS6 170.......... LEDS7 169.......... LEDLATCH 168.......... LEDCLK 167.......... TRST 166.......... TCK 165.......... TMS 164.......... TDO 163.......... TDI 162.......... SD4/TP4 161.......... SD5/TP5 160.......... SD6/TP6 159.......... SD7/TP7 158.......... GNDA 157.......... TPFIP7 GNDD....... 1 N/C....... 2 TXD7....... 3 RXD7....... 4 N/C....... 5 N/C....... 6 N/C....... 7 TXD6....... 8 RXD6....... 9 N/C....... 10 N/C....... 11 N/C....... 12 N/C....... 13 N/C....... 14 VCCIO....... 15 GNDD....... 16 TXD5....... 17 RXD5....... 18 N/C....... 19 N/C....... 20 N/C....... 21 TXD4....... 22 RXD4....... 23 N/C....... 24 N/C....... 25 N/C....... 26 N/C....... 27 N/C....... 28 N/C....... 29 TXD3....... 30 VCCIO....... 31 GNDD....... 32 RXD3....... 33 N/C....... 34 N/C....... 35 N/C....... 36 TXD2....... 37 RXD2....... 38 N/C....... 39 N/C....... 40 N/C....... 41 N/C....... 42 N/C....... 43 N/C....... 44 N/C....... 45 N/C....... 46 N/C....... 47 GNDD....... 48 GNDD....... 49 GNDD....... 50 GNDD....... 51 VCCIO....... 52 Part # LOT # FPO # LXT9782HC XX XXXXXX XXXXXXXX Rev # 156 .......... TPFIN7 155 .......... VCCR 154 .......... TPFOP7 153 .......... TPFON7 152 .......... GNDA 151 .......... TPFON6 150 .......... TPFOP6 149 .......... VCCT 148 .......... VCCR 147 .......... TPFIN6 146 .......... TPFIP6 145 .......... GNDA 144 .......... GNDA 143 .......... TPFIP5 142 .......... TPFIN5 141 .......... VCCR 140 .......... TPFOP5 139 .......... TPFON5 138 .......... GNDA 137 .......... TPFON4 136 .......... TPFOP4 135 .......... VCCT 134 .......... VCCR 133 .......... TPFIN4 132 .......... TPFIP4 131 .......... GNDA 130 .......... GNDA 129 .......... TPFIP3 128 .......... TPFIN3 127 .......... VCCR 126 .......... VCCT 125 .......... TPFOP3 124 .......... TPFON3 123 .......... GNDA 122 .......... TPFON2 121 .......... TPFOP2 120 .......... VCCR 119 .......... TPFIN2 118 .......... TPFIP2 117 .......... GNDA 116 .......... GNDA 115 .......... TPFIP1 114 .......... TPFIN1 113 .......... VCCR 112 .......... VCCT 111 .......... TPFOP1 110 .......... TPFON1 109 .......... GNDA 108 .......... TPFON0 107 .......... TPFOP0 106 .......... VCCR 105 .......... TPFIN0 Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT9782 is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order. 10 GNDD....... 53 TXD1....... 54 RXD1....... 55 N/C....... 56 N/C....... 57 N/C....... 58 TXD0....... 59 RXD0....... 60 N/C....... 61 N/C....... 62 N/C....... 63 N/C....... 64 N/C....... 65 N/C....... 66 VCCIO....... 67 GNDD....... 68 N/C....... 69 MDC....... 70 MDIO....... 71 GNDD....... 72 GNDD....... 73 GNDD....... 74 GNDD....... 75 TxSLEW_0....... 76 TxSLEW_1....... 77 GNDS....... 78 PAUSE....... 79 VCCD....... 80 GNDD....... 81 PWRDWN....... 82 RESET....... 83 MDINT....... 84 MDDIS....... 85 GNDD....... 86 VCCD....... 87 VCCD....... 88 VCCD....... 89 SYNC....... 90 GNDD....... 91 REFCLK....... 92 ADD_0....... 93 ADD_1....... 94 ADD_2....... 95 ADD_3....... 96 ADD_4....... 97 SD3/TP3....... 98 SD2/TP2....... 99 SD1/TP1....... 100 SD0/TP0....... 101 RBIAS....... 102 GNDA....... 103 TPFIP0....... 104 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 3. LXT9782BC (PBGA) Preliminary Pin Assignments 1 A B C D E F G H J K L M N P R T U V W Y NC 2 NC 3 QCLK 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TRST SD6/ TP6 SD5/ TP5 SD7/ TP7 VCCT TP FIN7 TP FON7 TP FOP6 TP FIP6 TP FIP7 TP FOP7 TP FON6 TP FIN6 LED/ LED/ LED/ LED/ LED/ LED/ LED/ GNDD CFG1_2 VCCD LEDS_4 LEDS_3 LEDS_7 CFG2_2 CFG3_1 CFG4_2 CFG5_2 CFG6_1 CFG7_3 LED/ LED/ QSTAT CFG0_1 LED/ CFG2_3 CFG3_3 LED/ LED/ VCCD CFG5_3 CFG6_2 LED CLK A B C D E F G H J K L M N P R T U V W Y NC GNDD NC GNDD VCCD LEDS_1 LEDS_5 TMS VCCT NC TXD7 RXD7 LED/ LED/ LED/ LED/ LED/ LED/ GNDD LEDS_2 LEDS_6 VCCIO CFG0_3 LED/ CFG2_1 CFG4_1 CFG6_3 CFG7_2 CFG7_1 CFG1_3 LED/ LED/ LED/ LED/ LED/ GNDD CFG0_2 CFG1_1 CFG3_2 CFG4_3 CFG5_1 LEDS _0 LED LATCH TDO SD4/ TP4 GNDA NC NC NC TXD6 VCCIO TDI TCK GNDA VCCR GNDA NC RXD6 NC GNDD VCCR GNDA VCCT VCCT NC NC NC NC GNDA GNDA TP FIN5 TP FON5 TP FOP4 TP FIN4 TP FIP5 TP FOP5 TP FON4 TP FIP4 VCCIO TXD5 GNDD GNDD GNDA GNDA NC RXD5 NC NC VCCR GNDA NC TXD4 NC NC GNDD GNDD GNDD GNDD VCCR GNDA RXD4 NC NC NC GNDD GNDD GNDD GNDD GNDA GNDA VCCT VCCT NC NC TXD3 NC GNDD GNDD GNDD GNDD GNDA GNDT GNDA VCCT VCCT VCCIO RXD3 GNDD GNDD GNDD GNDD GNDD GNDD VCCR GNDA TP FIN3 TP FON3 TP FOP2 TP FIP2 TP FIP3 TP FOP3 TP FON2 TP FIN2 NC NC NC TXD2 VCCR GNDA NC RXD2 NC NC GNDA GNDA NC NC NC NC GNDA GNDA NC NC NC GNDD VCCR GNDA VCCT VCCT NC NC NC NC GNDD NC NC GNDD NC TxSLEW_1 GNDD MDINT SD1/ TP1 SD2/ TP2 SD3/ TP3 GNDA VCCR GNDA TP FIN1 TP FON1 TP FOP0 TP FIP0 TP FIP1 TP FOP1 TP FON0 TP FIN0 VCCIO TXD1 NC NC RXD0 NC NC MDC NC GNDS GNDD RESET ADD_2 ADD_1 ADD_3 SD0/ TP0 RBIAS GNDA NC RXD1 NC TXD0 GNDD NC NC MDIO NC PAUSE GNDD PWRDWN GNDD SYNC ADD_0 ADD_4 GNDA VCCT NC NC NC NC NC VCCIO NC TxSLEW_0 VCCD VCCD VCCD MDDIS GNDD GNDD REFCLK VCCD VCCD VCCT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1. Ports 6 and 7 are available only on the LXT9782. These ports are not bonded out on the LXT9762. Datasheet 11 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 4. LXT9762HC (PQFP) Preliminary Pin Assignments 208 .......... VCCIO 207 .......... QCLK 206 .......... QSTAT 205 .......... LED/CFG0_3 204 .......... LED/CFG0_2 203 .......... LED/CFG0_1 202 .......... LED/CFG1_3 201 .......... LED/CFG1_2 200 .......... LED/CFG1_1 199 .......... LED/CFG2_3 198 .......... LED/CFG2_2 197 .......... LED/CFG2_1 196 .......... N/C 195 .......... N/C 194 .......... N/C 193 .......... VCCIO 192 .......... GNDD 191 .......... N/C 190 .......... N/C 189 .......... N/C 188 .......... LED/CFG3_3 187 .......... LED/CFG3_2 186 .......... LED/CFG3_1 185 .......... LED/CFG4_3 184 .......... LED/CFG4_2 183 .......... LED/CFG4_1 182 .......... LED/CFG5_3 181 .......... LED/CFG5_2 180 .......... LED/CFG5_1 179 .......... VCCD 178 .......... GNDD 177 .......... LEDS0 176 .......... LEDS1 175 .......... LEDS2 174 .......... LEDS3 173 .......... LEDS4 172 .......... LEDS5 171 .......... LEDS6 170 .......... LEDS7 169 .......... LEDLATCH 168 .......... LEDCLK 167 .......... TRST 166 .......... TCK 165 .......... TMS 164 .......... TDO 163 .......... TDI 162 .......... N/C 161 .......... SD5/TP3 160 .......... SD6/TP4 159 .......... SD7/TP5 158 .......... GNDA 157C 161 .......... SD5/TP3 160 .......... SD6/TP4 159 .......... SD7/TP5 158 .......... GNDA 157 .......... TPFIP5 GNDD .......1 N/C .......2 TXD5 .......3 RXD5 .......4 N/C .......5 N/C .......6 N/C .......7 TXD4 .......8 RXD4 .......9 N/C .......10 N/C .......11 N/C .......12 N/C .......13 N/C .......14 VCCIO .......15 GNDD .......16 TXD3 .......17 RXD3 .......18 N/C .......19 N/C .......20 N/C .......21 N/C .......22 N/C .......23 N/C .......24 N/C .......25 N/C .......26 N/C .......27 N/C .......28 N/C .......29 N/C .......30 VCCIO .......31 GNDD .......32 N/C .......33 N/C .......34 N/C .......35 N/C .......36 TXD2 .......37 RXD2 .......38 N/C .......39 N/C .......40 N/C .......41 N/C .......42 N/C .......43 N/C .......44 N/C .......45 N/C .......46 N/C .......47 GNDD .......48 GNDD .......49 GNDD .......50 GNDD .......51 VCCIO .......52 Part # LOT # FPO # LXT9762HC XXXXXX XXXXXXXX Rev 156.......... TPFIN5 155.......... VCCR 154.......... TPFOP5 153.......... TPFON5 152.......... GNDA 151.......... TPFON4 150.......... TPFOP4 149.......... VCCT 148.......... VCCR 147.......... TPFIN4 146.......... TPFIP4 145.......... GNDA 144.......... GNDA 143.......... TPFIP3 142.......... TPFIN3 141.......... VCCR 140.......... TPFOP3 139.......... TPFON3 138.......... GNDA 137.......... N/C 136.......... N/C 135.......... N/C 134.......... N/C 133.......... N/C 132.......... N/C 131.......... N/C 130.......... N/C 129.......... N/C 128.......... N/C 127.......... N/C 126.......... N/C 125.......... N/C 124.......... N/C 123.......... GNDA 122.......... TPFON2 121.......... TPFOP2 120.......... VCCR 119.......... TPFIN2 118.......... TPFIP2 117.......... GNDA 116.......... GNDA 115.......... TPFIP1 114.......... TPFIN1 113.......... VCCR 112.......... VCCT 111.......... TPFOP1 110.......... TPFON1 109.......... GNDA 108.......... TPFON0 107.......... TPFOP0 106.......... VCCR 105.......... TPFIN0 1. Ports 6 and 7 are available only on the LXT9782. These ports are not bonded out on the LXT9762. Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT9762 is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order. 12 GNDD .......53 TXD1 .......54 RXD1 .......55 N/C .......56 N/C .......57 N/C .......58 TXD0 .......59 RXD0 .......60 N/C .......61 N/C .......62 N/C .......63 N/C .......64 N/C .......65 N/C .......66 VCCIO .......67 GNDD .......68 N/C .......69 MDC .......70 MDIO .......71 GNDD .......72 GNDD .......73 GNDD .......74 GNDD .......75 TxSLEW_0 .......76 TxSLEW_1 .......77 GNDS .......78 PAUSE .......79 VCCD .......80 GNDD .......81 PWRDWN .......82 RESET .......83 MDINT .......84 MDDIS .......85 GNDD .......86 VCCD .......87 VCCD .......88 VCCD .......89 SYNC .......90 GNDD .......91 REFCLK .......92 ADD_0 .......93 ADD_1 .......94 ADD_2 .......95 ADD_3 .......96 ADD_4 .......97 N/C .......98 SD2/TP2 .......99 SD1/TP1 .......100 SD0/TP0 .......101 RBIAS .......102 GNDA .......103 TPFIP0 .......104 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 1. 9762 Pin# PQFP LXT97x2 Serial MII Signal Descriptions 9782 Pin# Symbol Type1 Signal Description2, 3 PQFP PBGA Serial MII Data Interface Pins 59 54 37 17 8 3 - - 60 55 38 18 9 4 - - 90 59 54 37 30 22 17 8 3 60 55 38 33 23 18 9 4 90 W4 V2 N4 L3 J2 G2 D4 C2 V5 W2 P2 M2 K1 H2 E2 C3 W14 TXD0 TXD1 TXD2 TXD3 I TXD4 TXD5 TXD6 TXD7 RXD0 RXD1 RXD2 RXD3 O RXD4 RXD5 RXD6 RXD7 SYNC I SMII Synchronization. The MAC must generate a SYNC pulse every 10 REFCLK cycles to synchronize the SMII. Reference Clock. The LXT97x2 requires a 125 MHz SMII reference clock input at this pin. Refer to Functional Description for detailed clock requirements. MII Control Interface Pins 3 Receive Data - Ports 0-7. These serial output streams provide data received from the network. LXT97x2 drives the data out synchronously to REFCLK. Transmit Data - Ports 0-7. These serial input streams provide data to be transmitted to the network. LXT97x2 clocks the data in synchronously to REFCLK. 92 92 Y15 REFCLK I 71 84 70 71 84 70 W8 U12 V8 MDIO MDINT MDC I/O OD I Management Data Input/Output. Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates status change. Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations. When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. 85 85 Y12 MDDIS I 1. Type Column Coding: I = Input, O = Output, OD = Open Drain. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. 3. The LXT97x2 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet 13 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 2. 9762 Pin# PQFP 101 100 99 161 160 159 - - LXT97x2 Signal Detect/TP Select Signal Descriptions 9782 Pin# Symbol Type1 Signal Description2 PQFP 101 100 99 98 162 161 160 159 PBGA V16 U13 U14 U15 C16 B17 A17 C17 SD0/TP0 SD1/TP1 SD2/TP2 SD3/TP3 SD4/TP4 SD5/TP5 SD6/TP6 SD7/TP7 I Signal Detect - Ports 0 - 7. Tying the SD/TPn pins High or to a PECL input sets bit 16.0 = 1 and the respective port is forced to FX mode. Do not enable Auto-Negotiation if FX mode is selected. In the absence of an active link, the pin must be pulled High to enable loopback in FX mode. Do not enable Auto-Negotiation if FX mode is selected. The SD/TPn pins have internal pull-downs. When not using FX mode, SD/TPn pins should be tied to GNDA. TP Select - Ports 0 - 7. Tying the SD/TPn pins Low sets bit 16.0 = 0 and forces the port to TP mode. The operating mode of each port can be set to 10BASE-T or 100BASE-TX, half- or full-duplex, and auto-negotiation or manual control via the hardware control interface pins as shown in Table 9 on page 27. 1. Type Column Coding: I = Input, O = Output. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. Table 3. 9762 Pin# PQFP 107, 108 111, 110 121, 122 140, 139 150, 151 154, 153 -, - -, - LXT97x2 Network Interface Signal Descriptions 9782 Pin# Symbol PQFP 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 PBGA W19,W20 V20, V19 P19, P20 N20, N19 H19, H20 G20, G19 C19, C20 B20, B19 TPFOP0, TPFON0 TPFOP1, TPFON1 TPFOP2, TPFON2 TPFOP3, TPFON3 O TPFOP4, TPFON4 TPFOP5, TPFON5 TPFOP6, TPFON6 TPFOP7, TPFON7 Twisted-Pair/Fiber Outputs, Positive & Negative Ports 0-7. During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFO pins produce differential PECL outputs for fiber transceivers. Type1 Signal Description 2 104, 105 115, 114 118, 119 143, 142 146, 147 157, 156 -, - -, - 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 Y19, Y20 TPFIP0, TPFIN0 U20, U19 TPFIP1, TPFIN1 R19, R20 TPFIP2, TPFIN2 M20, M19 J20, J19 F20, F19 TPFIP3, TPFIN3 TPFIP4, TPFIN4 TPFIP5, TPFIN5 I Twisted-Pair/Fiber Inputs, Positive & Negative - Ports 0-7. During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential 100BASETX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFI pins receive differential PECL inputs from fiber transceivers. D19, D20 TPFIP6, TPFIN6 A20, A19 TPFIP7, TPFIN7 1. Type Column Coding: I = Input, O = Output. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. 14 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 4. 97x21 Pin# PQFP 163 164 165 166 167 LXT97x2 JTAG Test Signal Descriptions 9782 Pin# Symbol Type2 Signal Description PBGA D14 C15 B16 D15 A16 TDI TDO TMS TCK TRST I / IP O I / IP I / ID I / IP Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for JTAG test (REFCLK). Test Reset. Reset input for JTAG test. 1. Pin numbers apply to both the LXT9762 and the LXT9782. 2. Type Column Coding: I = Input, O = Output, OD = Open Drain, IP = Weak Internal Pull-up, ID = Weak Internal Pull-down. Table 5. 97x21 Pin# LXT97x2 Miscellaneous Signal Descriptions Symbol Type2 Signal Description3 Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: PQFP PBGA 76 77 Y8 U10 TxSLEW_0 TxSLEW_1 I TxSLEW_1 0 0 1 1 TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 2.5 ns 3.1 ns 3.7 ns 4.3 ns 79 W10 PAUSE I I I Pause. Setting this pin High causes LXT97x2 to advertise Pause capabilities on all ports during auto-negotiation. Power Down. When High, forces LXT97x2 into Power-Down mode. This pin is OR'ed with the Power-Down bit (0.11). Refer to discussion on page 28 and to Table 38 on page 66 for more information. Reset. This active Low input is OR'ed with the control register Reset bit (0.15). When held Low, outputs are forced to inactive state. 82 W12 PWRDWN 83 V12 RESET 1. Pin numbers apply to both the LXT9762 and the LXT9782. 2. Type Column Coding: A = Analog, I = Input, O = Output, OD = Open Drain. 3. The LXT97x2 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet 15 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 5. 97x21 Pin# LXT97x2 Miscellaneous Signal Descriptions (Continued) Symbol Type2 Signal Description3 PQFP PBGA 97 96 95 94 93 W16 V15 V13 V14 W15 ADD_4 ADD_3 ADD_2 ADD_1 ADD_0 I I I I I Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. Port 0 Address = Base + 0. Port 1 Address = Base + 1. Port 2 Address = Base + 2. Port 3 Address = Base + 3. Port 4 Address = Base + 4. Port 5 Address = Base + 5. Port 6 Address = Base + 6 (LXT9782 Only). Port 7 Address = Base + 7 (LXT9782 Only). Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k 1% resistor. Quick Status. Provides for continuous PHY status updates, without the need for constant polling. Quick Clock. Clock used for sending out QSTAT information. Maximum frequency is 25 MHz. 102 206 207 V17 B4 A3 RBIAS QSTAT QCLK AI O I 1. Pin numbers apply to both the LXT9762 and the LXT9782. 2. Type Column Coding: A = Analog, I = Input, O = Output, OD = Open Drain. 3. The LXT97x2 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Table 6. LXT97x2 Power Supply Signal Descriptions 97x21 Pin# Symbol Type Signal Description Digital Power Supply - Core. +3.3V supply for core digital circuits. Digital Power Supply - I/O Ring. +3.3V supply for digital I/O circuits. Regardless of the IO supply, digital I/O pins remain tolerant of 5V signal levels. Analog Power Supply. +3.3V supply for all analog receive circuits. PQFP 80, 87, 88, 89, 179 PBGA A12, B11, B12, Y9, Y10, Y11, Y16, Y17 C4, D5, G1, M1, Y6, V1 D17, E17, H17, J17, M17, N17, T17, U17 A18, B18, E19, E20, K19, K20, L19, L20, T19, T20, W18, Y18 VCCD VCCIO VCCR VCCT - 15, 31, 52, 67, 193, 208 106, 113, 120, 127, 134, 141, 148, 155 LXT9762 and LXT9782: 112, 149 LXT9782 Only: 126, 135 - - - Analog Power Supply. +3.3V supply for all analog transmit circuits. 1, 16, 32, 48-51, 53, 68, 72-75, 81, 86, 91, 178, 192 A4, B2, B8, C12, D11, E4, G3, G4, J9 - J12, K9 - K12, L9 - L12, M3, M4, M9 - M12, T4, U5, U8, U11, V11, W5, W11, W13, Y13, Y14 - GNDD Digital Ground. Ground return for both core and I/O digital supplies (VCCD and VCCIO). 1. Unless otherwise noted, pin numbers apply to both the LXT9762 and the LXT9782. 16 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 6. LXT97x2 Power Supply Signal Descriptions (Continued) 97x21 Pin# Symbol Type Signal Description PQFP PBGA C18, D16, D18, E18, F17, F18, G17, G18, H18, J18, K17, K18, L17, L18, M18, N18, P17, P18, R17, R18, T18, U16, U18, V18, W17 - Analog Ground. Ground return for analog supply. All ground pins can be tied together using a single ground plane. LXT9762 and LXT9782: 103, 109, 116, 117, 123, 138, 144, 145, 152, 158 LXT9782 Only: 130, 131 78 GNDA V10 GNDS - Substrate Ground. Ground for chip substrate. 1. Unless otherwise noted, pin numbers apply to both the LXT9762 and the LXT9782. Table 7. 9762 Pin# PQFP 177 176 175 174 173 172 171 170 168 169 LXT97x2 LED Signal Descriptions Symbol Type1 Signal Description2 9782 Pin# PQFP 177 176 175 174 173 172 171 170 168 169 PBGA D12 B13 C13 A14 A13 B14 C14 A15 B15 D13 LEDS_0 LEDS_1 LEDS_2 LEDS_3 O LEDS_4 LEDS_5 LEDS_6 LEDS_7 LEDCLK LEDLATCH O O LED Clock. 1 MHz clock for LED serial data output. LED Latch. Framing signal for serial LED outputs. Port 0 LED Drivers 1 -3. These pins drive LED indicators for Port 0. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 0 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 1 LED Drivers 1 -3. These pins drive LED indicators for Port 1. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 1 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Serial LEDs 0 - 7. Each serial LED output indicates a particular status condition for every port. Bit 0 is assigned to Port 0, bit 1 is assigned to Port 1, etc. There are 8 possible LEDs per port, for a total of 48 display LEDs. However, typical equipment designs use no more than 3 LEDs per port, selected by the designer. Using per-event, rather than per-port outputs reduces the number of serial shift registers required. Instead of requiring an external serial-to-parallel shift register for each port, this method requires only one per LED type, reducing board space and component costs. Refer to "Serial LED Functions" on page 40 for details. 203 204 205 203 204 205 B5 D6 C5 LED/CFG0_1 LED/CFG0_2 LED/CFG0_3 I OD OS 200 201 202 200 201 202 D7 A5 C6 LED/CFG1_1 LED/CFG1_2 LED/CFG1_3 I OD OS 1. Type Column Coding: I = Input, O = Output, OD = Open Drain, OS = Open Source. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. Datasheet 17 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 7. 9762 Pin# PQFP LXT97x2 LED Signal Descriptions (Continued) Symbol Type1 Signal Description2 9782 Pin# PQFP PBGA Port 2 LED Drivers 1 -3. These pins drive LED indicators for Port 2. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 2 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 3 LED Drivers 1 -3. These pins drive LED indicators for Port 3. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 3 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 4 LED Drivers 1 -3. These pins drive LED indicators for Port 4. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 4 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 5 LED Drivers 1 -3. These pins drive LED indicators for Port 5. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 5 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 6 LED Drivers 1 -3. These pins drive LED indicators for Port 6. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 6 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). Port 7 LED Drivers 1 -3. These pins drive LED indicators for Port 7. Each output indicates one of several available status conditions as selected by the LED Configuration Register (refer to Table 51 on page 75 for details). Port 7 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 27 for details). 197 198 199 197 198 199 C7 A6 B6 LED/CFG2_1 LED/CFG2_2 LED/CFG2_3 I OD OS 186 187 188 194 195 196 A7 D8 B7 LED/CFG3_1 LED/CFG3_2 LED/CFG3_3 I OD OS 183 184 185 189 190 191 C8 A8 D9 LED/CFG4_1 LED/CFG4_2 LED/CFG4_3 I OD OS 180 181 182 186 187 188 D10 A9 B9 LED/CFG5_1 LED/CFG5_2 LED/CFG5_3 I OD OS - - - 183 184 185 A10 B10 C9 LED/CFG6_1 LED/CFG6_2 LED/CFG6_3 I OD OS - - - 180 181 182 C11 C10 A11 LED/CFG7_1 LED/CFG7_2 LED/CFG7_3 I OD OS 1. Type Column Coding: I = Input, O = Output, OD = Open Drain, OS = Open Source. 2. Ports 6 and 7 are available only on the LXT9782. These pins are not bonded out on the LXT9762. 18 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 8. 97x2 Pin# PQFP LXT9762 and LXT9782: 2, 5-7, 10-14, 19-21, 24-29, 34-36, 39-47, 56-58, 61-66, 69 LXT9762 Only: 98, 124 - 137, 162, 189 - 191, 194 - 196 Unused Pins 9782 Pin# Symbol PBGA A1,A2, B1, B3, C1, D1 - D3, E1, E3, F1 - F4, H1, H3, H4, J1, J3, J4, K2 - K4, L1, L2, L4, N1 - N3, P1, P3, P4, R1 R4, T1 - T3, U1 - U4, U6, U7, U9, V3, V4, V6, V7, V9, W1, W3, W6, W7, W9, Y1 - Y5, Y7 Type Signal Description N/C - No Connection - LXT97x2. These pins are not used on either the LXT9762 or LXT9782 and should not be connected. N/C - No Connection - LXT9762 Only. These additional pins are not used on the LXT9762 and should not be connected. Datasheet 19 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 2.0 2.1 Functional Description Introduction The LXT9782 eight-port Fast Ethernet 10/100 Transceiver supports 10 Mbps and 100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. Each port directly drives either a 100BASE-TX line (up to 100 meters) or a 10BASE-T line (up to 185 meters). The LXT9782 also supports 100BASE-FX operation via a Pseudo-ECL (PECL) interface. The LXT9762 offers the same features and functionality in a six-port device. This data sheet uses the singular designation "LXT97x2" to refer to both devices. 2.1.1 OSPTM Architecture Intel's LXT97x2 incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This improves receiver noise and cross-talk performance. The OSP signal processing scheme requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines clocked at speeds up to 125 MHz. Logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT97x2 provides improved data recovery, EMI performance, and power consumption. 2.1.2 Comprehensive Functionality The LXT97x2 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT97x2 reads its configuration pins to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. The LXT97x2 provides half-duplex and fullduplex operation at 100 Mbps and 10 Mbps. If the PHY device on the other side of the link supports auto-negotiation, the LXT97x2 will autonegotiate with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support autonegotiation, the LXT97x2 will automatically detect the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. 20 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 The LXT97x2 provides an individual serial MII (SMII) for each network port. The SMII ports provide for communication between the Media Access Controllers (MACs) and the network ports. The SMII bit stuffing protocol is automatically set once the network port operating conditions have been determined Figure 5. LXT97x2 Interfaces LXT97x2 TXDn TPFOPn TPFONn SMII DATA I/F RXDn SYNC REFCLK TPFIPn TPFINn Network I/F MDIO Mgmt I/F H/W Config Mgmt I/F & Port LEDs Serial LED I/F Quick Status I/F MDIO MDC MDINT MDDIS VCC LED/CFGn_n LEDS_n LEDLATCH LEDCLK ADD<4:0> QSTAT QCLK RBIAS 22.1k VCCIO VCCD GNDD .01uF +3.3V +3.3V 2.2 2.2.1 Interface Descriptions 10/100 Network Interface The LXT97x2 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. Refer to Table 2 on page 14 for specific pin assignments. The LXT97x2 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX PECL output. When not transmitting data, the LXT97x2 generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input, depending on the mode selected. The interface speed is determined by auto-negotiation/parallel detection or manual control. 2.2.1.1 Twisted-Pair Interface When operating at 100 Mbps, the LXT97x2 continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT97x2 generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Datasheet 21 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII The LXT97x2 supports either 100BASE-TX or 10BASE-T connections over 100, Category 5, Unshielded Twisted Pair (UTP) cable. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit. On the transmit side, Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 5 on page 15) allow the designer to match the output waveform to the magnetic characteristics. 2.2.1.2 Fiber Interface The LXT97x2 provides a PECL interface suitable for driving a fiber-optic coupler. The PECL interface complies with the ANSI X3.166 specification. Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control Interface or MDIO registers. 2.2.2 SMII Data Interface The LXT97x2 provides six or eight independent SMII ports with a common reference clock and SYNC signal, as well as an MDIO management interface. The SMII Data Interface exchanges data between the LXT97x2 and up to eight Media Access Controllers (MACs). 2.2.3 Configuration Management Interface The LXT97x2 provides both a Hardware Control Interface (via the LED/CFG pins) and an MDIO interface for device configuration and management. 2.2.3.1 Hardware Control Interface The LXT97x2 provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins for each port. Refer to the discussion in the Initialization section for additional details. 2.2.3.2 MDIO Management Interface The LXT97x2 supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the LXT97x2. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. Additional registers allow for expanded functionality. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write operations are disabled and the Hardware Control Interface provides primary configuration control. When MDDIS is Low, the MDIO port is enabled for both read and write operations and the Hardware Control Interface is not used. The timing for the MDIO Interface is shown in Table 33 on page 61. MDIO read and write cycles are shown in Figure 7 (read) and Figure 8 (write). 22 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 MII Addressing The protocol allows one controller to communicate with multiple LXT97x2 chips. Pins ADD_<4:0> determine the base address. Each port adds its port number (0 through n) to the base address to obtain its port address as shown in Figure 6. Figure 6. Port Address Scheme BASE ADDR (ex. ADDR=4) LXT9782 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 PHY ADDR (BASE+0) ex. 4 PHY ADDR (BASE+1) ex. 5 PHY ADDR (BASE+2) ex. 6 PHY ADDR (BASE+3) ex. 7 PHY ADDR (BASE+4) ex. 8 PHY ADDR (BASE+5) ex. 9 PHY ADDR (BASE+6) ex. 10 PHY ADDR (BASE+7) ex. 11 1. Ports 6 and 7 not available on the LXT9762. Figure 7. Management Interface Read Frame Structure MDC MDIO (Read) High Z 32 "1"s Preamble 0 ST 1 1 0 Op Code A4 A3 PHY Address A0 R4 R3 R0 Z 0 D15 D15D14 D14 D1 D1 D0 Data Read Idle Register Address Turn Around Write Datasheet 23 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 8. Management Interface Write Frame Structure MDC MDIO Write) Idle 32 "1"s Preamble 0 ST 1 0 1 Op Code A4 A3 PHY Address A0 R4 R3 R0 1 0 Turn Around D15 D14 Data D1 D0 Idle Register Address Write MII Interrupts The LXT97x2 provides a single interrupt pin available to all ports. Interrupt logic is shown in Figure 9. The LXT97x2 also provides two dedicated interrupt registers for each port. Register 18 (Table 49 on page 73) provides interrupt enable and mask functions and Register 19 (Table 50 on page 74) provides interrupt status. Setting bit 18.1 = 1, enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT97x2. However, because it is a shared interrupt, it does not indicate which port is requesting service. Interrupts may be caused by five conditions: * * * * * Receive Monitor counter full Auto-negotiation complete Speed status change Duplex status change Link status change Figure 9. Interrupt Logic Event X Enable Reg AND Event X Status Reg Per Event Force Interrupt Interrupt Enable . . . OR AND Per port . . . Port Combine Logic Interrupt Pin 1. Interrupt (Event) Status Register is cleared on read. 2. X = Any Interrupt capability 24 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 2.3 2.3.1 Operating Requirements Power Requirements The LXT97x2 requires four power supply inputs, VCCD, VCCR, VCCT and VCCIO. The digital and analog circuits require 3.3 V supplies (VCCD, VCCR and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground. An additional supply may be used for the SMII (VCCIO). VCCIO should be supplied from the same power source used to supply the controller on the other side of the SMII interface. Refer to Table 20 on page 54 for the SMII I/O characteristics. As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 23 on page 49. 2.3.2 2.3.2.1 Clock Requirements Reference Clock The LXT97x2 requires a constant 125 MHz reference clock (REFCLK). The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e, PLL-based) to minmize transmit jitter. Refer to Table 21 on page 54 for clock timing requirements. 2.3.2.2 SYNC Signal The LXT97x2 requires a 12.5 MHz input pulse for SMII synchronization. See"SYNC Pulse" on page 31 2.3.2.3 Serial LED Clock The LXT97x2 requires a 1 MHz clock input to synchronize the serial LED output. 2.3.2.4 Quick Status Clock The LXT97x2 requires a clock input (up to 25 MHz) to synchronize the Quick Status output. 2.4 Initialization When the LXT97x2 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control Interface pins or by an MDIO write operation as shown in Figure 10. The following modes are available using either Hardware Control or MDIO Control: * Force network link to 100FX (Fiber). * Force network link operation to: -- 100TX, Full-Duplex Datasheet 25 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- 100TX, Half-Duplex -- 10BASE-T, Full-Duplex -- 10BASE-T, Half-Duplex * Allow auto-negotiation / parallel-detection. When the network link is forced to a specific configuration, the LXT97x2 immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT97x2 begins the auto-negotiation / parallel-detection operation. Figure 10. Initialization Sequence Power-up or Reset Read H/W Control Interface Initialize MDIO Registers MDIO Control Mode Low MDDIS Voltage Level? Hardware Control Mode High Pass Control to MDIO Interface (Read/Write) Disable MDIO Read and Write Operations Software Reset? Yes Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 2.4.1 Hardware Configuration Settings The LXT97x2 provides a hardware option to set the initial device configuration. The LED/CFG drivers can operate as either open drain or open source circuits as shown in Figure 11. This provides three control bits per port, as listed in Table 9. In applications where all ports configured the same, several pins may be tied together with a single resistor. 26 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 11. Hardware Control Settings VCC Configuration Bit = 1 LED/CFG Pin LED/CFG Pin Configuration Bit = 0 1. LEDs will automatically correct their polarity upon power-up or reset. . Table 9. Hardware Configuration Settings Pin Settings LED/CFGn_1 Resulting Register Bit Values Control Register AutoNeg 0.12 Speed 0.13 0 Full 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 Half 100 Full Half 100 1 0 1 1 Half 10/100 Full 1 1 1 1 0 1 0 0 0 1 1 0 1 0 0 Full 1 1 0 1 0 0 1 FD 0.8 0 XXXX2 Auto-Negotiation Advertisement AN Advertisement Register 100FD 4.8 100TX 4.7 10 FD 4.6 10T 4.5 Desired Configuration AutoNeg Mode Speed Mode Duplex Mode Half 1 0 2 0 3 0 10 Disabled Enabled 3 1. These pins set the default values for registers 0 and 4 accordingly. 2. X = Don't Care. 3. Do not select Fiber mode with Auto-Negotiation enabled. 2.4.2 Reset The LXT97x2 provides both hardware and software resets. Configuration control of AutoNegotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to Table 38 on page 66). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset will not be detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0). Datasheet 27 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 2.4.3 Power-Down Mode The LXT97x2 offers both global and per-port power-down modes. 2.4.3.1 Global (Hardware) Power Down The global power-down mode is controlled by PWRDWN pin 82 (PQFP) or pin W12 (PBGA). When PWRDWN is High, the following conditions are true: * * * * * 2.4.3.2 All LXT97x2 ports and clock are shut down. All outputs are tri-stated. All weak pad pull-up and pull-down resistors are disabled. The MDIO registers are not accessible. The MDIO registers are reset after power down. Port Power Down Individual port power-down control is provided by bit 0.11 in the respective port Control Registers (refer to Table 38 on page 66). During individual port power-down, the following conditions are true: * The individual port is shut down. * The MDIO registers remain accessible. * The MDIO registers are unaffected. 2.5 2.5.1 Link Establishment Auto-Negotiation The LXT97x2 attempts to auto-negotiate with its counter-part across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "page". All devices that support auto-negotiation must implement the "Base Page" defined by IEEE 802.3 (Registers 4 and 5). LXT97x2 also supports the optional `Next Page' function (Registers 7 and 8). 2.5.1.1 Base Page Exchange By exchanging Base Pages, the LXT97x2 and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds the highest common capabilities that both sides support. Both sides then exchange more pages, and finally agree on the operating state of the line. 2.5.1.2 Next Page Exchange Additional information, above that required by base page exchange is also sent via "Next Pages'. The LXT97x2 fully supports the 802.3 method of negotiation via Next Page exchange. 28 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 2.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: * After power-up, power-down, or reset, the power-down recovery time, as specified in Table 34 on page 62, must be exhausted before proceeding. * Set the auto-negotiation advertisement register bits. * Enable auto-negotiation (set MDIO bit 0.12 = 1). Do not enable Auto-Negotiation if fiber mode is selected. Figure 12. Link Establishment Process Power-Up, Reset, Link Failure Start Disable Auto-Negotiation 0.12 = 0 Check Value 0.12 0.12 = 1 Enable Auto-Neg/Parallel Detection Go To Forced Settings Attempt AutoNegotiation Listen for 100TX Idle Symbols Listen for 10T Link Pulses Done YES Link Set NO 2.5.2 Parallel Detection In parallel with auto-negotiation, the LXT97x2 also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT97x2 to communicate with devices that do not support auto-negotiation. 2.6 Serial MII Operation The LXT97x2 exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions: * Conveys complete MII information between a 10/100 PHY and MAC with two pins per port. Datasheet 29 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII * Allows a multi-port MAC/PHY communication with one system clock. * Operates in both half and full duplex. * Supports per-packet switching between 10 Mbps and 100 Mbps data rates. The Serial MII operates at 125 MHz using a global reference clock and frame synchronization signal (REFCLK and SYNC). Each port has an individual two-line data interface (TXDn and RXDn). All signals are synchronous to REFCLK. Figure 13 is a simple SMII block diagram and Table 10 summarizes the SMII signals. Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times. Table 10. SMII Signal Summary Signal TXD RXD SYNC REFCLK To PHY MAC PHY MAC & PHY From MAC PHY MAC System Purpose Receive data & control Transmit data & control Synchronization Synchronization 1. Refer to Table 1 on page 13 for detailed signal descriptions. Figure 13. Simplified SMII Application Diagram 8 8 TX RX SYNC LXT9782 16 Port MAC Clock 8 8 TX RX SYNC CLOCK LXT9782 30 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 . Figure 14. 100Mbps Serial MII Data Flow Strip TX_EN & TX_ER Status Bits Serial Data Stream To/From S0 S1 D0 D1 D2 MAC 2 Nibbles Tx/Rx Data D0 D1 D2 D3 4B/5B 2 Symbols Tx/Rx Data S0 S1 S2 S3 S4 To/From PMD Sublayer D3 D4 D5 D6 D7 Insert CRS & RX_DV Status Bits D0 D1 D2 D3 S0 S1 S2 S3 S4 2.6.1 Reference Clock REFCLK operates at 125 MHz. The transmit and receive data and control streams must always be synchronized to REFCLK by the MAC and PHY. The LXT97x2 samples these signals on the rising edge of REFCLK. 2.6.2 SYNC Pulse The SYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must continuously generate a SYNC pulse once every 10 REFCLK cycles. The SYNC pulse signals the start of each new segment as shown in Figure 15 and Figure 17. 2.6.3 Transmit Data Stream Transmit data and control information are signalled in ten bit segments. In 100 Mbps mode each segment contains a new byte of data. In 10 Mbps mode the MAC must repeat a 10M serial word on TXD ten times. LXT97x2 may sample that serial word at any point. The SYNC pulse signals the start of a new segment as shown in Figure 15. 2.6.3.1 Transmit Enable The MAC must assert the TX_EN bit in each segment of TXData, and de-assert TX_ENn after the last segment of the packet. 2.6.3.2 Transmit Error In 100BASE-x mode when the MAC asserts the TX_ER bit, the LXT97x2 will drive "H" symbols onto the network interface. TX_ER does not have any function in 10M operation. Datasheet 31 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 15. Serial MII Transmit Synchronization CLOCK SYNC TX TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TX_ER 2.6.4 Receive Data Stream Receive data and control information are signalled in ten bit segments. In 100 Mbps mode each segment contains a new byte of data. In 10 Mbps mode each segment is repeated ten times (except for the CRS bit) and the MAC can sample any one of the ten segments. 2.6.4.1 Carrier Sense The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS bit is set in real time, even in 10 Mbps mode. (All other bits are repeated in 10 sequential segments). 2.6.4.2 Receive Data Valid The LXT97x2 asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion timing changes depend on line operating speed: * For 100TX and 100FX links, the RX_DV bit is asserted from the first nibble of preamble to the last nibble of the data packet. * For 10BT links, the entire preamble is truncated. The RX_DV bit is asserted with the first nibble of the Start-of-Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet. 2.6.4.3 Receive Error In 100BASE-X mode when the LXT97x2 receives an errored symbol from the network, it drives "1110" on the associated RXD pin. 2.6.4.4 Receive Status Encoding The LXT97x2 encodes status information onto the RXD line during IPG as listed in Table 11 on page 33. Status bit RXD<5> indicates the validity of the upper nibble (RXD<7:4> of the last byte of the previous frame). RXD and RX_DV are passed through the internal elasticity FIFO to smooth any clock rate differences between the recovered clock and the 125 MHz reference clock. 32 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 2.6.5 Loopback A test loopback function is available for 100 Mbps SMII testing. Bit 0.14 must be set High for correct operation. When data is looped back, whatever the MAC transmits is looped back in its entirety, including the preamble. In FX mode, the respective SD/TPn pin must be pulled High to enable loopback. Figure 16. Loopback Paths LXT97x2 FX Driver SMII Digital Block 100X Loopback Analog Block TX Driver 2.6.6 Collision The SMII interface does not provide a collision output and relies on the MAC to interpret COL conditions using CRS and TX_EN. CRS is unaffected by the transmit path. Figure 17. Serial MII Receive Synchronization CLOCK SYNC RXD0 RXER RXD1 Speed RXD2 Duplex RXD3 Link RXD4 Jabber RXD5 Valid RXD6 RXD6 RXD7 RXD7 RX CRS RX_DV CRS Table 11. RX Status Encoding Bit Definitions Signal CRS RX_DV RX_ER (RXD0) SPEED (RXD1) DUPLEX (RXD2) Definition Carrier Sense - identical to MII, except that it is not an asynchronous signal. Receive Data Valid - identical to MII. When RX_DV = 0, status information is transmitted to the MAC. When RX_DV = 1, received data is transmitted to the MAC. Inter-frame status bit RXD0 indicates whether or not the PHY detected an error somewhere in the previous frame. Inter-frame status bit RXD1 indicates port operating speed. Inter-frame status bit RXD2 indicates port duplex condition. 0 = Status Byte 1 = Valid Data Byte 0 = No Error 1 = Error 0 = 10Mbps 1 = 100Mbps 0 = Half 1 = Full 1. Both RXD0 and RXD5 bits are valid in the segment immediately following a frame, and remain valid until the first data segment of the next frame begins. Datasheet 33 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 11. RX Status Encoding Bit Definitions (Continued) Signal LINK (RXD3) JABBER (RXD4) VALID (RXD5) RXD) RXD7 Definition Inter-frame status bit RXD3 indicates port link status. Inter-frame status bit RXD4 indicates port jabber status. Inter-frame status bit RXD5 conveys the validity of the upper nibble of the last byte of the previous frame. Reserved This bit is set to 1. 0 = Down 1 = Up 0 = OK 1 = Error 0 = Invalid 1 = Valid Ignore Always = 1 1. Both RXD0 and RXD5 bits are valid in the segment immediately following a frame, and remain valid until the first data segment of the next frame begins. 2.7 2.7.1 100 Mbps Operation 100BASE-X Network Operations During 100BASE-X operation, the LXT97x2 transmits and receives 5-bit symbols across the network link. Figure 18 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT97x2 sends out Idle symbols on the line. In 100TX mode, the LXT97x2 scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are descrambled and decoded and sent across the MII to the MAC. In 100FX mode, the LXT97x2 transmits and receives NRZI signals across the PECL interface. An external 100FX transceiver module is required to complete the fiber connection. As shown in Figure 18, the MAC starts each transmission with a preamble pattern. As soon as the LXT97x2 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT97x2 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to transmitting Idle symbols. Figure 18. 100BASE-X Frame Format 64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets) P0 P1 P6 SFD DA DA SA SA L1 L2 D0 D1 Dn CRC I0 IFG Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD) Start-of-Frame Delimiter (SFD) Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD) 34 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 2.7.2 .100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT97x2 is a Physical Layer 1 (PHY) device. The LXT97x2 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss LXT97x2 operation from the reference model point of view. 2.7.2.1 PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function described in Table 12 on page 36. For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function. 10T operation does not use the 4B/5B encoder. Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data according to the 4B/5B coding rules until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. Dribble Bits The LXT97x2 handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble is passed across the SMII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble is not sent onto the SMII bus. Datasheet 35 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 19. Protocol Sublayers MII Interface PCS Sublayer LXT97x2 Encoder/Decoder Serializer/De-serializer PMA Sublayer Link/Carrier Detect PECL Interface PMD Sublayer Scrambler/ De-scrambler Fiber Transceiver 100BASE-TX 100BASE-FX Table 12. 4B/5B Coding Code Type 4B Code 3210 0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 Name 0 1 2 3 4 5 6 7 8 9 A B C 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Interpretation 1101 1110 1. 2. 3. 4. D E 11011 11100 Data D Data E The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. 36 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 12. 4B/5B Coding (Continued) Code Type 4B Code 3210 Name 5B Code 43210 Interpretation 1111 IDLE undefined 0101 CONTROL 0101 undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined undefined undefined 1. 2. 3. 4. F I 1 11101 1 1 1 11 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Data F Idle. Used as inter-stream fill code Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2 Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid J2 K2 T3 R3 H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. 2.7.2.2 PMA Sublayer Link In 100 Mbps mode, the LXT97x2 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. If the scrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100M idle patterns do not bring up a 10M link. The LXT97x2 reports link failure via the MII status bits (1.2, 17.10, and 19.4) and interrupt functions. If auto-negotiate is enabled, link failure causes the LXT97x2 to re-negotiate. Datasheet 37 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Link Failure Override The LXT97x2 normally transmits 100 Mbps data packets or Idle symbols only when the link is up, and transmits only FLP bursts when the link is not up. Setting bit 16.14 = 1 overrides this function, allowing the LXT97x2 to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT97x2 automatically begins transmitting FLP bursts if the link goes down. Carrier Sense For 100TX and 100FX links, a Start-of-Stream Delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without / T/R; however, in this case the RX_ER bit in the RX Status Frame is asserted for one clock cycle when CRS is de-asserted. * For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an End-of-Frame (EOF) marker. Receive Data Valid The LXT97x2 asserts the RX_DV bit when it receives a valid packet. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller. 2.7.2.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/Descrambler (100TX Only) The scrambler spreads the signal power spectrum and reduces EMI using an 11-bit, non-datadependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. The scrambler is automatically bypassed when the fiber interface is enabled. Scrambler bypass provides diagnostic and test support. Baseline Wander Correction The LXT97x2 provides a baseline wander correction function, making the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT97x2 baseline wander correction characteristics allow the LXT97x2 to recover error-free data while receiving worst-case "killer" packets over all cable lengths. 38 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Polarity Correction The LXT97x2 automatically detects and corrects for receive signal (TPIP/N) inversion. Reversed polarity is detected if eight inverted link pulses, or four inverted EOF markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity converter resets to a non-inverted state. Fiber PMD Sublayer The LXT97x2 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT97x2 uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications. Far End Fault Indications The LXT97x2 Signal Detect pins receive signal fault indications from local fiber transceivers via the SD pins. The device can also detect far end fault code in the received data stream. The LXT97x2 "ORs" both fault conditions to set bit 1.4. Bit 1.4 is set once and clears when read. Either fault condition causes the LXT97x2 to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2. * When bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT97x2 transmits far end fault code if fault conditions are detected by the Signal Detect pins. * When bit 16.2 = 0, the LXT97x2 does not transmit far end fault code. It continues to transmit idle code and may or may not drop link depending on the setting for bit 16.14. 2.8 10 Mbps Operation The LXT97x2 operates as a standard 10BASE-T transceiver. Data transmitted by the MAC is Manchester-encoded, and transmitted on the TPOP/N outputs. Received data is decoded and passed to the MAC. The LXT97x2 supports all the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT97x2 transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT97x2 sends out link pulses on the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT97x2 and sent across the MII to the MAC. The LXT97x2 does not support fiber connections at 10 Mbps. Datasheet 39 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 2.8.1 10T Preamble Handling The LXT97x2 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when 16.5 = 0, the LXT97x2 strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT97x2 are the SFD "5D" hex followed by the body of the packet. In 10T mode with 16.5 = 1, the LXT97x2 passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10T loopback, the LXT97x2 loops back whatever the MAC transmits to it, including the preamble. 2.8.2 10T Dribble Bits The LXT97x2 device handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble is passed across the SMII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble is not sent onto the SMII bus. 2.8.3 10T Link Test In 10T mode, the LXT97x2 always transmit link pulses. If the Link Test function is enabled, it monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, data transmission is disabled. If the Link Test function is disabled, the LXT97x2 transmits to the connection regardless of detected link pulses. Link Test can be disabled by setting bit 16.14 = 1. 2.8.3.1 Link Failure Link failure occurs if Link Test is enabled and no link pulses or packets are received. If this condition occurs, the LXT97x2 returns to the link establishment mode selected at initialization. 2.8.4 10T Jabber If a transmission exceeds the jabber timer, the LXT97x2 disables the transmit and loopback functions. The LXT97x2 automatically exits jabber mode after the unjab time has expired. The jabber timer can be disabled by setting bit 16.10 = 1. 2.9 2.9.1 Monitoring Operations Serial LED Functions The LXT97x2 provide eight serial LED outputs (LEDS7:0) which may be attached to external HC595-type shift registers (refer to Figure 26 on page 52). The LEDCLK signal is used to shift data into the 595's internal shift register. The LEDLATCH signal is used to latch data from the 595's internal shift register to the 595's internal storage register. The LXT97x2 drives the LEDSn and LEDLATCH outputs on the falling edge of LEDCLK. All serial LEDs will be stretched in accordance with bits 20.1 and 20.3:2. 40 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Each serial output reports a specific status condition for all ports. Ports 0 through 7 are assigned bits 0:7 in each stream (bits 3 and 4 are not used on the LXT9762). The serial outputs report the following conditions for each port: * LEDS0 Serial Output indicates Activity 0 = Active1 = Inactive * LEDS1 Serial Output indicates Polarity (10 Mbps) 0 = Switched Polarity1 = Normal Polarity * LEDS2 Serial Output indicates Duplex (D) 0 = Full Duplex1 = Half Duplex * LEDS3 Serial Output indicates Link 0 = Link active1 = Link inactive * LEDS4 Serial Output indicates Collision 0 = Collision active1 = Collision inactive * LEDS5 Serial Output indicates Receive 0 = Receive active1 = Receive inactive * LEDS6 Serial Output indicates Transmit 0 = Transmit active1 = Transmit inactive * LEDS7 Serial Output indicates Speed 0 = 100 Mbps1 = 10 Mbps Datasheet 41 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 20. Serial LED Streams LEDCLK (1 MHz) LEDS(0) LEDS(1) LEDS(2) LEDS(3) LEDS(4) LEDS(5) activity (port 0) activity (port 1) activity (port 2) polarity (port 2) activity (port 3) activity (port 4) polarity (port 4) activity (port 5) activity (port 6) activity (port 7) activity (port 0) activity (port 1) activity (port 2) activity (port 3) activity (port 4) activity (port 5) polarity (port 0) polarity (port 1) polarity (port 3) polarity (port 5) polarity (port 6) polarity (port 7) polarity (port 0) polarity (port 1) polarity (port 2) polarity (port 3) polarity (port 4) polarity (port 5) duplex (port 0) link (port 0) duplex (port 1) duplex (port 2) duplex (port 3) duplex (port 4) duplex (port 5) duplex (port 6) duplex (port 7) link (port 7) duplex (port 0) duplex (port 1) duplex (port 2) link (port 2) duplex (port 3) duplex (port 4) duplex (port 5) link (port 1) link (port 2) link (port 3) link (port 4) link (port 5) link (port 6) link (port 0) link (port 1) link (port 3) link (port 4) link (port 5) collision (port 0) receive (port 0) collision collision (port 1) (port 2) collision collision collision collision collision (port 3) (port 4) (port 5) (port 6) (port 7) collision collision collision collision (port 0) (port 1) (port 2) (port 3) collision collision (port 4) (port 5) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) receive (port 6) receive (port 7) receive (port 0) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) LEDS(6) LEDS(7) LEDLATCH transmit transmit transmit transmit transmit transmit transmit transmit (port 0) (port 1) (port 2) (port 3) (port 4) (port 5) (port 6) (port 7) speed (port 0) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) speed (port 6) speed (port 7) transmit transmit transmit (port 0) (port 1) (port 2) transmit transmit transmit (port 3) (port 4) (port 5) speed (port 0) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) Spare on LXT9762 Spare on LXT9762 Alternate Port Positions for LXT9762 LEDS(0:7) Port 5 Port 0 Port 1 Port 2 Spare Spare Port 3 Port 4 Port 5 Port 0 Port 1 Port 2 Spare Spare Port 3 2.9.2 Per-Port LED Driver Functions The LXT97x2 incorporates three direct drive LEDs per port. On power up, all the LEDs outputs are asserted for approximately 1 second after Reset is de-asserted. Each LED driver can be programmed to indicate one of several status conditions using the LED Configuration Register. Each per-port LED can be programmed (refer to Table 51 on page 75) to indicate one the following conditions: * * * * * * Operating Speed Transmit Activity Receive Activity Collision Condition Link Status Duplex Mode The LEDs can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications: * If Link is down LED is off. * If Link is up LED is on. 42 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 * If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits 20.3:2 and continues to blink as long as activity is present. The LED driver pins also provide manual configuration control during Hardware Control operation. Refer to the discussion of "Hardware Control Interface" on page 22 for details. 2.9.2.1 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, the pulse stretch time will be further extended. When an event such as receiving a packet occurs it will be edge detected and it will start the stretch timer. The LED driver will remain asserted until the stretch timer expires. If another event occurs before the stretch timer expires then the stretch timer will be reset and the stretch time will be extended. When a long event (such as duplex status) occurs it will be edge detected and it will start the stretch timer. When the stretch timer expires the edge detector will be reset so that a long event will cause another pulse to be generated from the edge detector which will reset the stretch timer and cause the LED driver to remain asserted. Figure 21 shows how the stretch operation functions. Figure 21. LED Pulse Stretching Event LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active Low. 2.9.3 Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: * Bit 17.7 is set to 1 once the auto-negotiation process is completed. * Bits 1.2 and 17.10 are set to 1 once the link is established. * Additional bits in Register 1 (refer to Table 39 on page 66) and Register 17 (refer to Table 48 on page 72) can be used to determine the link operating conditions and status. 2.9.3.1 Monitoring Next Page Exchange The LXT97x2 offers an Alternate Next Page mode to simplify the next page exchange process. Normally, bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled (16.1 = 1), bit 6.1 is automatically cleared whenever a new negotiation process takes place. This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT97x2 uses bit 6.5 to indicate Datasheet 43 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Bits 6.1 and 6.5 are cleared when read. 2.9.4 Using the Quick Status Register The LXT97x2 continuously sends out the Quick Status Register contents on the QSTAT pin. This output provides a continuous, real-time status update of several different LXT97x2 attributes and modes including RX, TX, COL and the auto-negotiation process. The 16 bits of the Quick Status Register are separated by a 16-bit signature frame (1111111111111111) to simplify interface designs. The LXT97x2 sources this status information separated by the signature with respect to the falling edge of the QCLK input. An ASIC need supply only 1 clock output (up to 25 MHz) for multiple PHY devices. Refer to Table 48 on page 72 for Quick Status bits descriptions. Figure 22. Quick Status Register 16 BIT SIGNATURE QSTAT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 QUICK STATUS REGISTER-Port 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (0) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 (0) D3 D2 D1 D0 Port 2 thru n-1 QUICK STATUS REGISTER-Port n D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (0) 1. QCLK is used to output the above information. 2. Bits D15 and D0 are always set to 0. (0) 2.10 Boundary Scan (JTAG1149.1) Functions LXT97x2 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible via boundary scan. 2.10.1 Boundary Scan Interface This interface consists of five pins (TMS,TDI,TDO, TCK and TRST). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is internally pulled down. TDO does not have an internal pull-up or pull-down. 44 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 2.10.2 State Machine The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset, the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is High for five TCK periods. 2.10.3 Instruction Register The IDCODE instruction is always invoked after the state machine resets. The decode logic ensures the correct data flow to the data registers according to the current instruction. Valid instructions are listed in Table 14. 2.10.4 Boundary Scan Register Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 13. Table 13. BSR Mode of Operation Mode 1 2 3 4 Description Capture Shift Update System Function Table 14. Supported JTAG Instructions Name EXTEST IDCODE SAMPLE High Z Clamp BYPASS Code 0000000000000000 1111111111111110 1111111111111110 1111111111001111 1111111111101111 1111111111111111 Description External Test ID Code Inspection Sample Boundary Force Float Clamp Bypass Scan BSR ID REG BSR Bypass BSR Bypass Data Register Table 15. Device ID Register 31:28 Version 0000 27:12 Part ID (hex) 2622 (LXT9762) 2636 (LXT9782) 11:8 Jedec Continuation Characters 0000 7:1 JEDEC ID1 111 1110 0 Reserved 1 1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110) which becomes 111 1110. Datasheet 45 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII 3.0 3.1 Application Information Design Recommendations The LXT97x2 complies with IEEE requirements and provides outstanding receive Bit Error Rate (BER) and long-line-length performance. Obtaining maximum performance from the LXT97x2 requires attention to detail and good design practices. Refer to the LXT97x2 Design and Layout Guide for detailed design and layout information. 3.1.1 General Design Guidelines Adhering to generally accepted design practices minimizes noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: * Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. * Use ample bulk and decoupling capacitors throughout the design (a value of .01 F is recommended for decoupling caps). * * * * * * Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. Do not route any digital signals between the LXT97x2 and the RJ-45 connectors at the edge of the board. edge of the board. Use this area for chassis ground, or leave it void. * Do not extend any circuit power and ground plane past the center of the magnetics or to the 3.1.2 Power Supply Filtering Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and degrade line performance. Minimize ground noise as much as possible using good general techniques and by filtering the VCC plane. Predicting the noise performance of any design is difficult, although certain factors greatly increase the risk of noise problems: * Poorly-regulated or over-burdened power supplies * Wide data busses (32-bits+) running at a high clock rate * DC-to-DC converters Intel recommends filtering the power supply to the analog VCC pins of the LXT97x2. This has two benefits. First, prevents digital switching noise from affecting the analog circuitry inside the LXT97x2, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. 46 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Intel recommends dividing the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT97x2. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one LXT97x2, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. Beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 F) should be place on each side of each bead. In addition, a high-frequency bypass cap (.01F) should be placed near each analog VCC pin. 3.1.3 Power and Ground Plane Layout Considerations Take great care when laying out the power and ground planes. The following guidelines are recommended: * Follow the guidelines in the LXT97x2 Design & Layout Guide for locating the split between the digital and analog VCC planes. * Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, away from the magnetics, and away from the RJ-45 connectors. * Place the layers so that the TPFOP/N and TPFIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N. 3.1.3.1 Chassis Ground For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2 kV isolation to the Bob Smith termination. 3.1.4 MII Terminations Series termination resistors are not required on the SMII signals driven by the LXT97x2. 3.1.5 The RBIAS Pin The LXT97x2 requires a 22.1 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. Surround the RBIAS trace with a filtered ground; do not run high-speed signals next to RBIAS. 3.1.6 The Twisted-Pair Interface Follow standard guidelines for a twisted-pair interface: * Keep transmit pair traces as short as possible; both traces should have the same length. Datasheet 47 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII * Avoid vias and layer changes as much as possible. * Keep the transmit and receive pairs apart to avoid cross-talk. * Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. * The output stage of the transmitter shown in Figure 24 on page 50 is designed to match the 100 characteristic impedance of an unshielded CAT5 twisted-pair wire. The external resistor that is typically required for impedance matching is integrated in the transmitter of the LXT97xx. The internal termination provides a constant current reference in both 10BASE-T and 100BASE-TX applications and meets all IEEE transmitter requirements such as return loss, while reducing external component requirements. It has no impact in fibre designs. * Some magnetic vendors are producing magnetics with improved return loss performance. Use of these improved magnetics increases the return loss budget available to the system designer. * Improve EMI performance by filtering the TPO center tap. A single ferrite bead may be used to supply center tap current to all ports. All ports draw a combined total of 520 mA so the bead should be rated at 780 mA. 3.1.6.1 Magnetics Information The LXT97x2 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 1.5 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 16 for transformer requirements. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. 3.1.7 The Fiber Interface The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic transceiver. The transmit and receive pair should be DC-coupled to the transceiver, and biased appropriately. Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 25 on page 51 shows a typical example. Table 16. Magnetics Requirements Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - 40 35 -16 Return Loss -10 - - dB 80 MHz Nom 1:1 1:1 0.6 - 1.5 - - - Max - - 1.1 - - - - - Units - - dB Test Condition H kV dB dB dB .1 to 60 MHz 60 to 100 MHz 30 MHz 48 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 3.2 Typical Application Circuits Figure 24 shows a typical layout of the LXT97x2 twisted-pair interface in a dual-high (stacked) RJ45 application. Figure 23. Power and Ground Supply Connections LXT97x2 GNDS RBIAS GNDA .01F .01F 10F 22.1k 1% VCCR VCCT Analog Supply Plane Ferrite Bead + Digital Supply Plane 10F VCCD .01F +3.3V GNDD .01F VCCIO + 3.3V Datasheet 49 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 24. Typical Twisted-Pair Interface TPFOP 1:1 RJ45 1 1 2 3 TPFON TPFIP 270 pF 5% 1:1 50 1% 50 50 4 50 5 6 LXT97x1 TPFIN 2 50 1% 50 50 7 50 8 270 pF 5% 0.01 F 3 * * * = 0.001 F / 2.0 kV 4 VCCT 0.1F .01F GNDA 5 1. The 100 transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive pair center-tap do not require a 2 kV termination. 3. Center tap current may be supplied from 3.3V VCCA as shown. However, additional power savings may be realized by supplying the center-tap from from a 2.5V current source. In either case a single ferrite bead (rated at 800 mA) may be used to supply center tap current to all ports. 4. Receive common mode bypass cap may improve BER performance in systems with noisy power supplies. 5. Recommended 0.1F capacitor to improve the EMI performance. 50 To Twisted-Pair Network Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 25. Typical Fiber Interface VCCD +3.3V 16 50 50 0.1 mF GNDD TPFONn TPFOPn VCCD +3.3V TDTD+ To Fiber Network LXT97x2 130 Fiber Txcvr SD 82 GNDD 130 130 VCCD +3.3V 0.1 mF GNDD SD/TPn 1 TPFINn TPFIPn 82 82 RDRD+ GNDD 1. Refer to fiber transceiver manufacturer's recommendations for termination circuitry. Example shown above is suitable for HFBR5900-series devices. Datasheet 51 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 26. Typical Serial LED Interface LEDLATCH 595 rclk Qa srclk ser Qh 595 LXT9782 LEDCLK LEDS(0) activity(7) activity(6) activity(5) activity(4) activity(3) activity(2) activity(1) activity(0) 595 LEDLATCH LEDCLK rclk Qa srclk leds(4) ser Qh collision(7) collision(6) collision(5) collision(4) collision(3) collision(2) collision(1) collision(0) See Detail for LXT9761 configuration. LEDLATCH LEDCLK LEDS(1) rclk srclk ser Qa Qh isopol(7) isopol(6) isopol(5) isopol(4) isopol(3) isopol(2) isopol(1) isopol(0) 595 LEDLATCH LEDCLK LEDS(5) rclk Qa srclk ser Qh receive(7) receive(6) receive(5) receive(4) receive(3) receive(2) receive(1) receive(0) 595 LEDLATCH LEDCLK LEDS(2) rclk Qa srclk ser Qh duplex(7) duplex(6) duplex(5) duplex(4) duplex(3) duplex(2) duplex(1) duplex(0) 595 LEDLATCH LEDCLK LEDS(6) rclk Qa srclk ser Qh transmit(7) transmit(6) transmit(5) transmit(4) transmit(3) transmit(2) transmit(1) transmit(0) 595 LEDLATCH LEDCLK LEDS(3) rclk Qa srclk ser Qh link(7) link(6) link(5) link(4) link(3) link(2) link(1) link(0) 595 LEDLATCH LEDCLK LEDS(7) rclk Qa srclk ser Qh speed(7) speed(6) speed(5) speed(4) speed(3) speed(2) speed(1) speed(0) Alternate Configuration for LXT9762 LEDLATCH LEDCLK 595 rclk Qa srclk ser Qh 1. Note: The outputs are always enabled on the hc595 chips. 2. Ports 6 and 7 are not available on the LXT9762. Serial outputs are re-mapped as shown in Detail at right. LEDS(0) activity(5) activity(4) activity(3) Not Used Not Used activity(2) activity(1) activity(0) 52 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 4.0 Test Specifications Table 17 through Table 34 and Figure 28 through Figure 39 represent the target specifications of the LXT97x2. These specifications are guaranteed by test, except where noted "by design." Minimum and maximum values listed in Table 19 through Table 34 apply over the recommended operating conditions specified in Table 18. Table 17. Absolute Maximum Ratings Parameter Supply voltage Operating temperature Ambient Case Storage temperature Sym VCC TOPA TOPC TST Min -0.3 -15 - -65 Max 4.0 +85 +120 +150 Units V C C C Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 18. Operating Conditions Parameter Ambient Recommended operating temperature Case Recommended supply voltage2 VCC current 4 Sym TOPA TOPC Vcca, Vccd Vccio ICC ICC ICC ICC ICC Min 0 0 3.15 3.15 - - - - - Typ1 - - 3.3 - 121 - - - 114.5 3 Max 70 122 3.45 3.45 140 140 - - - Units C C V V mA mA mA mA mA Analog & Digital I/O 100BASE-TX 100BASE-FX 10BASE-T Power Down Mode Auto-Negotiation 1. 2. 3. 4. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Voltages with respect to ground unless otherwise specified. Per port @ 3.3V. Environmental Condition - Natural convection (still air). Topc should be measured in the worst case thermal condition (chassis, application, environment). If the Topc is greater than 122C, Air Flow (`100 LFM) or heat sink (Attach: Thermoset WP100 tape, 1"x1" square with a 0.75" diameter phase-change dot. Heat Sink: Thermally 31x31 mm-sq low profile, P/N 22370B must be added. Alternate thermal solutions may be used and/or required depending on specific system conditions. Datasheet 53 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 19. Digital I/O Characteristics 1 Parameter Input Low voltage3 Input High voltage Input current Output Low voltage Output High voltage 3 Sym VIL VIH II VOL VOH Min - 2.0 -100 - 2.4 Typ2 - - - - - Max 0.8 - 100 0.4 - Units V V Test Conditions - - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA A V V 1. Applies to all pins except SMII pins. Refer to Table 20 for SMII I/O Characteristics. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 3. Does not apply to REFCLK, QCLK or TCK. Refer to Table 21 for clock input levels. Table 20. Digital I/O Characteristics - SMII Pins Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage VOH Driver output resistance (Line driver output enabled) RO RO 2 2 Sym VIL VIH II VOL VOH Min - 2.0 -100 - 2.2 2.0 - - Typ1 - - - - - - 100 100 Max 0.8 - 100 0.4 - - - - Units V V - - Test Conditions A V V V 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA, VCC = 3.3V IOH = -4 mA, VCC = 2.5V VCC = 2.5V VCC = 3.3V 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. Table 21. Required REFCLK and SYNC Characteristics Parameter Input Low voltage Input High voltage Input rise/fall time REFCLK frequency REFCLK clock frequency tolerance REFCLK clock duty cycle2 2 Sym VIL VIH Trf F Min - 2.0 - - - 40 Typ1 - - 1 125 - - Max 0.8 - - - 100 60 Units V V ns MHz ppm % Test Conditions - - - - - - f Tdc 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 54 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 22. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Sym VP Vss TRF TRFS - VO Min 0.95 98 3.0 - - - Typ1 - - - - - - Max 1.05 102 5.0 0.5 +/- 0.5 5 Units V % ns ns ns % Test Conditions Note 2 Note 2 Note 2 Note 2 Offset from 16ns pulse width at 50% of pulse peak - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Table 23. 100BASE-FX Transceiver Characteristics Parameter Note: Peak differential output voltage (single ended) Note: Signal rise/fall time Note: Jitter (measured differentially) Note: Peak differential input voltage Note: Common mode input range Sym VOP TRF - VIP VCMIR Min 0.6 - - 0.55 - Typ1 - - - - - Max 1.5 1.9 1.4 1.5 VCC - 0.7 Units V ns ns V V 10 <-> 90% - - - Test Conditions - 2.0 pF load 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 24. 10BASE-T Transceiver Characteristics Parameter Peak differential output voltage Link transmit period Transmit timing jitter added by the MAU and PLS sections 3, 4 Link min receive timer Link max receive timer Time link loss receive Differential squelch threshold 1. 2. 3. 4. 5. Sym VOP - - TLRmin TLRmax TLL VDS Min 2.2 8 0 2 50 50 - Typ1 2.5 - 2 4 64 64 390 Max 2.8 24 11 7 150 150 - Units V ms ns ms ms ms mV Peak Test Conditions Note 2 - Note 5 - - - 5 MHz square wave input Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Parameter is guaranteed by design; not subject to production testing. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. After line model specified by IEEE 802.3 for 10BASE-T MAU Datasheet 55 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 27. MII Sync Timing SYNC t1 t2 REFCLK Table 25. MII Sync Timing Parameters Parameter SYNC setup to REFCLK rising edge SYNC delay from REFCLK rising edge Sym t1 t2 Min 1.5 1 Typ1 - - Max - - Units ns ns Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 28. 100BASE-TX Receive Timing REFCLK t1 t2 RXD TPFI Table 26. 100BASE-TX Receive Timing Parameters Parameter RXD setup from REFCLK rising edge RXD Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de-asserted Sym t1 t2 - - Min 2 - - - Typ1 - 3 16 20 Max 5 - - - Units ns ns BT BT Test Conditions See Figure 29 - Synchronous sampling of SMII Synchronous sampling of SMII 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 56 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 29. SMII Output Delay Test Setup t1 measurement 1ns trace delay RXD DUT LXT9762/82 Ref Clk 1 CMOS Load ~ 6pF Figure 30. 100BASE-TX Transmit Timing REFCLK t1 TXD t2 TPFO Table 27. 100BASE-TX Transmit Timing Parameters Parameter TXD setup to REFCLK rising edge TXD hold from REFCLK rising edge TXEN sampled to start of /J/ Sym t1 t2 - Min 1.5 1 - Typ1 - - 12 Max - - - Units ns ns BT Test Conditions - - Synchronous sampling of SMII 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 57 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 31. 100BASE-FX Receive Timing REFCLK t1 t2 RXD TPFI Table 28. 100BASE-FX Receive Timing Parameters Parameter RXD setup from REFCLK rising edge RXD Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de-asserted Sym t1 t2 - - Min 2 - - - Typ1 - 3 16 20 Max 5 - - - Units ns ns BT BT Test Conditions See Figure 29 - Synchronous sampling of SMII Synchronous sampling of SMII 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 32. 100BASE-FX Transmit Timing REFCLK t1 TXD t2 TPFO Table 29. 100BASE-FX Transmit Timing Parameters Parameter TXD setup to REFCLK rising edge TXD hold from REFCLK rising edge TXEN sampled to start of /J/ Sym t1 t2 - Min 1.5 1 - Typ1 - - 12 Max - - - Units ns ns BT Test Conditions - - Synchronous sampling of SMII 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 58 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 33. 10BASE-T Receive Timing REFCLK t1 t2 RXD TPFI Table 30. 10BASE-T Receive Timing Parameters Parameter RXD setup from REFCLK rising edge RXD Rise/Fall Time Receive Start-of-Frame to CRS asserted Receive Start-of-Idle to CRS de-asserted Sym t1 t2 - - Min 2 - - - Typ1 - 3 9 12 Max 5 - - - Units ns ns BT BT Test Conditions See Figure 29 - Synchronous sampling of SMII2 Synchronous sampling of SMII2 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Assumes each SMII segment is sampled for CRS. Figure 34. 10BASE-T Transmit Timing REFCLK t1 TXD t2 TPFO Table 31. 10BASE-T Transmit Timing Parameters Parameter TXD setup to REFCLK rising edge TXD hold from REFCLK rising edge TXEN sampled to Start-of-Frame Sym t1 t2 - Min 1.5 1 - Typ1 - - 8 Max - - - Units ns ns BT Test Conditions - - Synchronous sampling of SMII 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 59 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 35. Auto-Negotiation and Fast Link Pulse Timing Clock Pulse Data Pulse Clock Pulse TPOP t1 t2 t3 t1 Figure 36. Fast Link Pulse Timing FLP Burst FLP Burst TPOP t4 t5 Table 32. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst Sym t1 t2 t3 t4 t5 - Min - 55.5 111 - 8 17 Typ1 100 - - 2 - - Max - 69.5 139 - 24 33 Units ns Test Conditions - - - - - - s s ms ms ea 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 60 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Figure 37. MDIO Write Timing (MDIO Sourced by MAC) MDC t1 (Min) t2 (Min) MDIO Figure 38. MDIO Read Timing (MDIO Sourced by PHY) MDC t3 MDIO Table 33. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA Sym t1 1 10 t2 1 t3 10 1 - - 130 - 300 - ns ns ns MDC = 8 MHz MDC = 2.5 MHz MDC = 8 MHz - - - - ns ns MDC = 8 MHz MDC = 2.5 MHz Min 10 Typ1 - Max - Units ns Test Conditions MDC = 2.5 MHz MDC to MDIO output delay, sourced by PHY 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 61 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 39. Power-Up Timing v1 VCC MDIO,etc t1 Table 34. Power-Up Timing Parameters Parameter Voltage threshold Power Up delay Sym v1 t1 Min - - Typ1 2.9 - Max - 500 Units V ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 40. Reset and Power-Down Recovery Timing RESET t1 t2 MDIO,etc Table 35. Reset and Power-Down Recovery Timing Parameters Parameter RESET pulse width RESET recovery delay Sym t1 t2 Min 10 - Typ1 - 1 Max - - Units ns ms Test Conditions 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 62 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 5.0 Register Definitions The LXT97x2 register set includes multiple 16-bit registers, 16 registers per port. Table 36 presents a complete register listing. Table 37 is a complete memory map of all registers and Table 38 through Table 53 provide individual register definitions. * Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation" sections of the IEEE 802.3 specification. * Additional registers (16 through 22) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions. Table 36. Register Set Address 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21-27 28 29 30 31 Control Register Status Register PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Next Page Receive Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Extended Status Register Port Configuration Register Quick Status Register Interrupt Enable Register Interrupt Status Register LED Configuration Register Reserved Transmit Control Register #1 Reserved Transmit Control Register #2 Reserved Refer to Table 53 on page 76 Refer to Table 52 on page 76 Register Name Bit Assignments Refer to Table 38 on page 66 Refer to Table 39 on page 66 Refer to Table 40 on page 67 Refer to Table 41 on page 68 Refer to Table 42 on page 68 Refer to Table 43 on page 69 Refer to Table 44 on page 70 Refer to Table 45 on page 71 Refer to Table 46 on page 71 Not Implemented Not Implemented Not Implemented Refer to Table 47 on page 72 Refer to Table 48 on page 72 Refer to Table 49 on page 73 Refer to Table 50 on page 74 Refer to Table 51 on page 75 Datasheet 63 Table 37. Register Bit Map Bit Fields Reg Title B15 Control Register Control Reset Status Register Status 100BaseT4 100Base- 100Base- 10Mbps Full X Half X Full Duplex Duplex Duplex MF 10Mbps 100Base- 100BaseA/N Remote T2 Half Extended Reserved Preamble Complete T2 Full Half Fault Status Suppress Duplex Duplex Duplex PHY ID Registers PHY ID 1 PHY ID2 PHY ID No 15 14 13 12 11 10 9 8 7 6 MFR Model No Auto-Negotiation Advertisement Register A/N Advertise Next Page Reserved Remote Reserved Fault Asymm Pause Pause 10Base-T 100Base- 100Base- 100BaseFull 10Base-T TX Full TX T4 Duplex Duplex Auto-Negotiation Link Partner Base Page Ability Register A/N Link Ability Ack Next Page Remote Reserved Fault Asymm Pause Pause 100BaseT4 100Base10Base-T 100BaseTX Full Full 10Base-T TX Duplex Duplex Auto-Negotiation Expansion Register Parallel Detect Fault Reserved Base Page Auto-Negotiation Next Page Transmit Register A/N Next Page Txmit Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field Auto-Negotiation Link Partner Next Page Ability Register A/N Link Next Page Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field Port Configuration Register Link Partner Next Page Able Next Page Able IEEE Selector Field IEEE Selector Field 5 4 3 2 1 MFR Rev No A/N Ability Link Status Jabber Detect Loopback Speed Select COL Test A/N Enable Power Down Reserved Re-start A/N Duplex Mode Speed Select Reserved B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Addr B0 0 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Extended Capability 1 0 2 3 4 5 A/N Expansion Page Received Link Partner A/N Able 6 7 8 64 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Bit Fields Reg Title B15 Link Disable Quick Status Register Quick Status Reserved Interrupt Enable Register Interrupt Enable Reserved Reserved Auto-Neg Mask Interrupt Status Register Interrupt Status Reserved Reserved Auto-Neg Done Speed Change LED Configuration Register LED Config LED1 LED2 Analog Test Register #1 Analog #1 Reserved Reserved Analog Test Register #2 Analog #2 Reserved Driver Amp Reserved Bandwidth Control LED3 LED Freq Pulse Stretch Duplex Change Speed Mask Duplex Mask Link Mask Reserved Reserved Interrupt Enable 10/100 Mode Link Transmit Receiver Status Status Collision Status Duplex Mode Auto-Neg Auto-Neg Complete Reserved Polarity Pause Error Bypass Bypass Txmit Scrambler 4B/5B Disable (100TX) (100TX) Jabber (10T) SQE (10T) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Addr B0 Port Config Reserved TP Remote Loopback Reserved FIFO Size PRE_EN Reserved Reserved Fault Enable (10T) Alternate Next Page Fiber Select 16 Reserved Reserved Reserved 17 Test Interrupt 18 MD Link Reserved Reserved Change Reserved Interrupt 19 Reserved/ Invalid Polarity 20 Slew Control 28 30 Datasheet 65 Table 37. Register Bit Map (Continued) LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 38. Control Register (Address 0) Bit 0.15 0.14 Reset Loopback 2 Name 1 = PHY reset 0 = normal operation 1 = enable loopback mode 0 = disable loopback mode 0.6 0.13 Speed Selection 1 1 0 0 0.13 1 = Reserved 0 = 1000 Mbps (not allowed) 1 = 100 Mbps 0 = 10 Mbps R/W Note 3 00 Description Type 1 R/W SC R/W Default 0 0 0.12 0.11 0.10 0.9 0.8 Auto-Negotiation Enable 4 Power Down Reserved Restart Auto-Negotiation Duplex Mode 1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process 1 = power down 0 = normal operation Write as zero. Ignore on read. 1 = Restart Auto-Negotiation Process 0 = normal operation 1 = Full Duplex 0 = Half Duplex This bit is ignored by the LXT97x2. 1 = Enable COL signal test 0 = Disable COL signal test 0.6 0.13 1 0 1 0 = Reserved = 1000 Mbps (not allowed) = 100 Mbps = 10 Mbps 1 1 0 0 R/W R/W R/W R/W SC R/W Note 3 0 0 0 Note 3 0 R/W 0 0.7 Collision Test 0.6 Speed Selection 1000 Mb/s R/W 00 0.5:0 Reserved Write as 0, ignore on Read R/W 00000 1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Internal Fiber Loopback Function is activated when the external SD/TP# pin for the port is pulled High. 3. Default value of bits 0.12, 0.13 and 0.8 are determined by hardware pins at Reset. Refer to Reset discussion on page 27. 4. Do not enable Auto-Negotiation if Fiber Mode is selected. Table 39. Status Register (Address 1) Bit 1.15 1.14 1.13 Name 100BASE-T4 100BASE-X Full Duplex 100BASE-X Half Duplex Description 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X Type 1 RO RO RO Default 0 1 1 1. RO = Read Only LL = Latching Low LH = Latching High 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. 66 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 39. Status Register (Address 1) (Continued) Bit 1.12 1.11 1.10 1.9 1.8 1.7 Name 10 Mbps Full Duplex 10 Mbps Half Duplex 100BASE-T2 Full Duplex 100BASE-T2 Half Duplex Extended Status Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault2 Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Description 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform half duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASE-T2 1 = Extended status information in register 15 0 = No extended status information in register 15 1 = ignore when read 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 1 = Auto-negotiation complete 0 = Auto-negotiation not complete 1 = Remote fault condition detected 0 = No remote fault condition detected 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = Jabber condition not detected 1 = Extended register capabilities 0 = Extended register capabilities Type 1 RO RO RO RO RO RO Default 1 1 0 0 0 0 1.6 RO 0 1.5 1.4 1.3 1.2 1.1 1.0 RO RO/LH RO RO/LL RO/LH RO 0 0 1 0 0 0 1. RO = Read Only LL = Latching Low LH = Latching High 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. Table 40. PHY Identification Register 1 (Address 2) Bit 2.15:0 Name PHY ID Number Description The PHY identifier composed of bits 3 through 18 of the OUI. Type 1 RO Default 0013 hex 1. RO = Read Only Datasheet 67 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 41. PHY Identification Register 2 (Address 3) Bit 3.15:10 3.9:4 3.3:0 Name PHY ID number Manufacturer's model number Manufacturer's revision number Description The PHY identifier composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number. 4 bits containing manufacturer's revision number. Type 1 RO RO RO Default 011110 001000 (LXT9762) 001011 (LXT9782) XXXX 1. RO = Read Only Figure 41. PHY Identifier Bit Mapping a b c r s x Organizationally Unique Identifier 1 2 3 0 0 1 3 18 19 24 I/G 15 0 15 10 9 4 3 0 PHY ID Register #1 (Address 2) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 PHY ID Register #2 (Address 3) 1 1 0 X X X X X X X X X X 0 0 0 2 B 7 5 0 3 0 00 20 7B The Level One OUI is 00207B hex. Manufacturer's Model Number Revision Number Table 42. Auto-Negotiation Advertisement Register (Address 4) Bit 4.15 4.14 4.13 4.12 4.11 Name Next Page Reserved Remote Fault Reserved Asymmetric Pause Description 1 = Port has ability to send multiple pages. 0 = Port has no ability to send multiple pages. Ignore. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. Type 1 R/W RO R/W R/W R/W R/W Default 1 0 0 0 0 Note 2 4.10 Pause 1 = Pause operation enabled for full-duplex links. 0 = Pause operation disabled. 1. R/W = Read/Write RO = Read Only LHR = Latches High on Reset 2. The default setting of bit 4.10 (PAUSE) is determined by pin 79. 3. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to Reset discussion on page 27. 68 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 42. Auto-Negotiation Advertisement Register (Address 4) (Continued) Bit Name Description Type 1 Default 4.9 100BASE-T4 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available. (The LXT97x2 does not support 100BASE-T4 but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) R/W 0 4.8 100BASETX full-duplex 100BASETX 10BASE-T full-duplex 10BASE-T Selector Field, S<4:0> 1 = Port is 100BASE-TX full duplex capable. 0 = Port is not 100BASE-TX full duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T full duplex capable. 0 = Port is not 10BASE-T full duplex capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations should not be transmitted. R/W Note 3 4.7 4.6 4.5 4.4:0 R/W R/W R/W R/W Note 3 Note 3 Note 3 00001 1. R/W = Read/Write RO = Read Only LHR = Latches High on Reset 2. The default setting of bit 4.10 (PAUSE) is determined by pin 79. 3. Default value of bits 4.8:5 are determined by hardware pins at Reset. Refer to Reset discussion on page 27. Table 43. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit 5.15 Name Next Page Description 1 = Link Partner has ability to send multiple pages. 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has received Link Code Word from LXT97x2. 0 = Link Partner has not received Link Code Word from the LXT97x2. 1 = Remote fault. 0 = No remote fault. Type 1 Default RO RO 0 0 5.14 Acknowledge 5.13 5.12 5.11 Remote Fault Reserved Asymmetric Pause RO RO RO 0 0 0 Ignore. Pause Operation defined in Clauses 40 and 27 1 = Link Partner is Asymmetric Pause capable. 0 = Link Partner is not Asymmetric Pause capable. 5.10 Pause 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. RO 0 1. RO = Read Only Datasheet 69 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 43. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit 5.9 5.8 5.7 5.6 5.5 Name 100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Description 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full duplex capable. 0 = Link Partner is not 100BASE-TX full duplex capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 100BASE-TX capable. 1 = Link Partner is 10BASE-T full duplex capable. 0 = Link Partner is not 10BASE-T full duplex capable. 1 = Link Partner is 10BASE-T capable. 0 = Link Partner is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations shall not be transmitted. Type 1 RO RO RO RO RO Default 0 0 0 0 0 5.4:0 Selector Field S<4:0> RO 00000 1. RO = Read Only Table 44. Auto-Negotiation Expansion (Address 6) Bit 6.15:6 Name Reserved Ignore on read. This bit indicates the status of the auto-negotiation variable, base page. It flags synchronization with the auto-negotiation state diagram allowing detection of interrupted links. This bit is only used if bit 16.1 (Alternate Next Page feature) is set. 1 = base_page = true 0 = base_page = false 6.4 6.3 6.2 Parallel Detection Fault Link Partner Next Page Able Next Page Able 1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred. 1 = Link partner is next page able. 0 = Link partner is not next page able. 1 = Local device is next page able. 0 = Local device is not next page able. 1 = Indicates that a new page has been received as and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of 802.3. This bit will be cleared on read. If bit 16.1 is set, the Page Received bit will also be cleared when mr_page_rx = false or transmit_disable = true. 1 = Link partner is auto-negotiation able. 0 = Link partner is not auto-negotiation able. RO LH RO RO 0 0 1 Description Type 1 RO Default 0 6.5 Base Page RO 0 6.1 Page Received RO LH 0 6.0 Link Partner A/ N Able RO 0 1. RO = Read Only LH = Latching High 70 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 45. Auto-Negotiation Next Page Transmit Register (Address 7) Bit 7.15 7.14 7.13 7.12 (NP) Name Next Page Reserved Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Additional next pages follow 0 = Last page Write as 0, ignore on read 1 = Message page 0 = Unformatted page 1 = Will comply with message. 0 = Can not comply with message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. Type 1 R/W RO R/W R/W Default 0 0 1 0 7.11 R/W 0 7.10:0 R/W 00000000 001 1. R/W = Read/Write RO = Read Only Table 46. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit 8.15 8.14 8.13 8.12 Name Next Page (NP) Acknowledge (ACK) Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field Description 1 = Link Partner has additional next pages to send. 0 = Link Partner has no additional next pages to send. 1 = Link Partner has received Link Code Word from LXT97x2. 0 = Link Partner has not received Link Code Word from LXT97x2. 1 = Page sent by the Link Partner is a Message Page. 0 = Page sent by the Link Partner is an Unformatted Page. 1 = Link Partner will comply with the message. 0 = Link Partner can not comply with the message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. Type 1 RO RO RO RO Default 0 0 0 0 8.11 RO 0 8.10:0 RO 0 1. RO = Read Only Note: Registers 9, 10 and 15 are not implemented. These registers only apply to 100BASE-T2 and 1000BASE-T, neither of which are supported by this device. Datasheet 71 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 47. Port Configuration Register (Address 16, Hex 10) Bit 16.15 16.14 16.13 16.12 16.11 16.10 Name Reserved Force Link Pass Transmit Disable Bypass Scramble (100BASE-TX) Reserved Jabber (10BASE-T) SQE (10BASE-T) TP Loopback (10BASE-T) Reserved Description This bit is ignored by the LXT97x2. 1 = Forces internal registers and state machines to Link Pass state. 0 = Normal operation. 1 = Disable Twisted-Pair transmitter. 0 = Normal Operation. 1 = Bypass Scrambler and Descrambler. 0 = Normal Operation. This bit is ignored by the LXT97x2. 1 = Disable Jabber. 0 = Normal operation. This bit is ignored by the LXT97x2. 1 = Enable Heart Beat. 0 = Disable Heart Beat. 1 = Disable TP loopback during half duplex operation. 0 = Normal Operation. This bit is ignored by the LXT97x2. 0 = FIFO allows packets up to 2 KBytes. 1 = FIFO allows packets up to 8 KBytes. Note: This assumes a 100 ppm difference between the reference clock and the recovered clock. 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD=preamble when CRS is asserted. Write as zero. Ignore on read. Write as zero. Ignore on read. 1 = Enable Far End Fault code transmission. 0 = Disable Far End Fault code transmission. 1 = Enable alternate auto-negotiate next page feature. 0 = Disable alternate auto-negotiate next page feature. 1 = Select fiber mode for this port. 0 = Select TP mode for this port. R/W 0 Type R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 16.9 16.8 16.7 R/W R/W 1 0 16.6 FIFO Size R/W 0 16.5 16.4 16.3 16.2 16.1 16.0 Preamble Enable Reserved Reserved Far End Fault Transmit Enable Alternate NP feature Fiber Select R/W R/W R/W R/W R/W R/W 0 0 0 1 0 Note 2 1. R/W = Read /Write 2. The default value of bit 16.0 is determined at Reset by the SD/TPn pin for the respective port. If SD/TPn is tied Low, the default value of bit 16.0 = 0. If SD/TPn is not tied Low, the default value of bit 16.0 = 1. Refer to Reset discussion on page 27. Table 48. Quick Status Register (Address 17, Hex 11) Bit 17.15 17.14 17.13 Name Reserved 10/100 Mode Transmit Status Always 0 1 = LXT97x2 is operating in 100BASE-TX mode. 0 = LXT97x2 is not operating 100BASE-TX mode. 1 = LXT97x2 is transmitting a packet 0 = LXT97x2 is not transmitting a packet Description Type 1 Default RO RO RO 0 0 0 1. RO = Read Only 72 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 48. Quick Status Register (Address 17, Hex 11) (Continued) Bit 17.12 17.11 17.10 17.9 17.8 Name Receive Status Collision Status Link Duplex Mode Auto-Negotiation Description 1 = LXT97x2 is receiving a packet 0 = LXT97x2 is not receiving a packet 1 = Collision is occurring 0 = No collision 1 = Link is up 0 = Link is down 1 = Full duplex 0 = Half duplex 1 = LXT97x2 is in Auto-Negotiation Mode 0 = LXT97x2 is in manual mode 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed This bit is only valid when auto-negotiate is enabled, and is equivalent to bit 1.5. Ignore 1= Polarity is reversed 0= Polarity is not reversed 1 = LXT97x2 is Pause capable 0 = LXT97x2 is not Pause capable This bit is equivalent to bit 4.10. 17:3 17:2:0 Error Reserved 1 = Error occurred (Remote Fault, X,Y,Z) 0 = No error occurred Ignore RO RO 0 0 Type 1 RO RO RO RO RO Default 0 0 0 0 0 17.7 Auto-Negotiation Complete Reserved Polarity RO 0 17.6 17.5 RO RO 0 0 17.4 Pause RO 1. RO = Read Only Table 49. Interrupt Enable Register (Address 18, Hex 12) Bit 18.15:8 18.7 Name Reserved ANMSK Write as 0; ignore on read. Mask for Auto-Negotiate Complete 1 = Enable event to cause interrupt 0 = Do not allow event to cause interrupt Mask for Speed Interrupt 18.6 SPEEDMSK 1 = Enable event to cause interrupt 0 = Do not allow event to cause interrupt Mask for Duplex Interrupt 18.5 DUPLEXMSK 1 = Enable event to cause interrupt 0 = Do not allow event to cause interrupt Mask for Link Status Interrupt 18.4 18.3 LINKMSK Reserved 1 = Enable event to cause interrupt 0 = Do not allow event to cause interrupt Write as 0, ignore on read. R/W R/W 0 0 R/W 0 R/W 0 R/W 0 Description Type 1 R/W Default N/A 1. R/W = Read /Write Datasheet 73 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 49. Interrupt Enable Register (Address 18, Hex 12) (Continued) Bit Name Description Type 1 Default 18.2 18.1 18.0 Reserved INTEN TINT Write as 0, ignore on read. 1 = Enable interrupts on this port. 0 = Disable interrupts on this port. 1 = Force interrupt on MDINT. 0 = Normal operation R/W R/W R/W 0 0 0 1. R/W = Read /Write Table 50. Interrupt Status Register (Address 19, Hex 13) Bit 19.15:8 19.7 Name Reserved ANDONE Ignore Auto-Negotiation Status 1= Auto-Negotiation has completed 0= Auto-Negotiation has not completed Speed Change Status 19.6 SPEEDCHG 1 = A Speed Change has occurred since last reading this register 0 = A Speed Change has not occurred since last reading this register Duplex Change Status 19.5 DUPLEXCHG 1 = A Duplex Change has occurred since last reading this register 0 = A Duplex Change has not occurred since last reading this register Link Status Change Status 19.4 19.3 19.2 19.1:0 LINKCHG Reserved MDINT Reserved 1 = A Link Change has occurred since last reading this register 0 = A Link Change has not occurred since last reading this register Ignore 1 = Indicates MII interrupt pending 0 = Indicates no MII interrupt pending Ignore RO/SC RO/SC RO 0 0 RO/SC 0 RO/SC 0 RO/SC 0 RO/SC N/A Description Type 1 RO Default N/A 1. R/W = Read/Write RO = Read Only SC = Self Clearing when read. 74 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 Table 51. LED Configuration Register (Address 20, Hex 14) Bit Name Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous)5 0110 = Reserved 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous)5 0110 = Reserved 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous)5 0110 = Reserved 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3,5 1111 = Reserved Type 1 Default LED1 20.15:12 Programming bits R/W 0000 LED2 20.11:8 Programming bits R/W 0100 LED3 20.7:4 Programming bits R/W 0010 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED may be active for a brief time after loss of link. Datasheet 75 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Table 51. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name Description 00 = Stretch LED events to 30 ms 01 = Stretch LED events to 60 ms 10 = Stretch LED events to 100 ms 11 = Reserved 0 = Disable pulse stretching of all LEDs 1 = Enable pulse stretching of all LEDs Type 1 Default 20.3:2 LEDFREQ R/W 00 20.1 20.0 PULSESTRETCH Reserved R/W R/W 1 0 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED may be active for a brief time after loss of link. Table 52. Transmit Control Register #1 (Address 28) Bit 28.12:4 Name Reserved Bandwidth Control Ignore. 00 = Nominal Differential Amp Bandwidth 01 = Slower 10 = Fastest 11 = Faster 00 = 2.5ns 01 = 3.1ns 10 = 3.7ns 11 = 4.3ns Description Type R/W Default N/A 28.3:2 R/W 00 28.1:0 Risetime Control R/W Note 2 1. RO = Read Only. R/W = Read/Write. 2. The default setting of bits 28.1:0 (Risetime) is determined by pins 91 and 94 TxSLEW<1:0>. Table 53. Transmit Control Register #2 (Address 30) Bit 30.15:14 30.13 30.12:0 Name Reserved Increase Driver Amplitude Reserved 1 = Increase Driver Amplitude 5% in all modes. 0 = Normal operation. Description Type R/W R/W R/W Default N/A 0 N/A 1. RO = Read Only. 76 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII -- LXT9762/9782 6.0 Package Specifications Figure 42. LXT97x2 PQFP Package Specification 208-Pin Plastic Quad Flat Package * Part Number LXT9762HC (6-port model) * Part Number LXT9782HC (8-port model) * Commercial Temperature Range (0C to 70C) D D1 Millimeters Dim Min A A1 e Max 4.10 3.60 0.27 30.90 28.30 30.90 28.30 .50 BASIC 0.25 3.20 0.17 30.30 27.70 30.30 27.70 E1 A2 E e b /2 D D1 E E1 2 L1 A A2 A1 L b 3 e L L1 q 0 5 5 0.50 0.75 1.30 REF 7 16 16 2 3 Datasheet 77 LXT9762/9782 -- Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII Figure 43. LXT97x2 PBGA Package Specification 272-Lead Plastic Ball Grid Array * Part Number LXT9782BC (8-port model) * Commercial Temperature Range (0C to 70C) 24.13 1.435 REF 1.27 27.00 0.20 24.00 0.20 8.00 0.10 PIN #A1 CORNER 0.75 0.15 A B C D E F G 1.27 PIN #A1 ID 8.00 0.10 H J K L 27.00 0.20 24.00 0.20 24.13 M N P R T U V W Y O1.00 (3 plcs) TOP VIEW 20 19 18 17 16 15 14 13 12 11 10 9 8 76 54 3 21 1.435 REF BOTTOM VIEW 0.92 0.05 2.13 0.19 NOTE: 1. ALL DIMENSIONS IN MILLIMETERS 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994 3. TOLERANCE = 0.05 UNLESS SPECIFIED OTHERWISE SEATING PLANE 0.61 0.04 0.60 0.10 SIDE VIEW 78 Datasheet |
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